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參數資料
| 型號： | MC12181D |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | 125 - 1000 MHZ FREQUENCY SYNTHESIZER |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1000 MHz, PDSO16 |
| 封裝： | PLASTIC, SO-16 |
| 文件頁數： | 1/9頁 |
| 文件大小： | 110K |
| 代理商： | MC12181D |
SEMICONDUCTOR
TECHNICAL DATA
125 – 1000 MHZ
FREQUENCY SYNTHESIZER
PIN CONNECTIONS
Order this document by MC12181/D
D SUFFIX
PLASTIC PACKAGE
CASE 751B
(SO–16)
1
16
16
1
15
2
14
3
13
4
A
OSCin
12
5
11
6
10
7
9
8
B
OSCout
C
VP
D
VCC
Pout
Do
Reset
GND
Rout
Fin
GND
Fin
(Top View)
Device
Operating
Temperature Range
Package
ORDERING INFORMATION
MC12181D
TA = –40
°
to +85
°
C
SO–16
The MC12181 is a monolithic bipolar synthesizer integrating a high
performance prescaler, programmable divider, phase/frequency detector,
charge pump, and reference oscillator/buffer functions. The device is
capable of synthesizing a signal which is 25 to 40 times the input reference
signal. The device has a 4–bit parallel interface to set the proper total
multiplication which can range from 25 to 40. When combined with an
external passive loop filter and VCO, the MC12181 serves as a complete
PLL subsystem.
2.7 to 5.5 V Operation
Low power supply current of 4.25 mA typical
On chip reference oscillator/buffer supporting wide frequency operating
range from 5 to 25 MHz
4–bit parallel interface for programming divider (N = 25 .... 40)
Wide 125 – 1000 MHz frequency of operation
Digital phase/frequency detector with linear transfer function
Balanced Charge Pump Output
Space efficient 16 lead SOIC package
Operating Temperature Range of –40 to 85
°
C
> 1000 V ESD Protection (I/O to Ground, I/O to VCC)
The device is suitable for applications where a fixed local oscillator (LO)
needs to be synthesized or where a limited number of LO frequencies need
to be generated. The device also has auxiliary open emitter outputs (Pout
and Rout) for observing the inputs to the phase detector for verification
purposes. In normal use the pins should be left open. The Reset input is
normally LOW. When this input is placed in the HIGH state the reference
prescaler is reset and the charge pump output (Do) is placed in the OFF
state.
The 4–bit programming interface maps into divider states ranging from 25
to 40. A is the LSB and D is the MSB. The data inputs (A,B,C, and D) are
CMOS compatible and have pull–up resistors. The inputs can be tied directly
to Vcc or Ground for programming or can be interfaced to an external data
latch/register. Table 1 below has a mapping of the programming states.
Table 1. Programming States
D
C
B
A
Divider
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Motorola, Inc. 1997
Rev 2
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