- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄382300 > MC12U128NACA (SAMSUNG SEMICONDUCTOR CO. LTD.) MultiMediaCard Specification PDF資料下載
參數(shù)資料
| 型號(hào)： | MC12U128NACA |
| 廠(chǎng)商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | MultiMediaCard Specification |
| 中文描述： | 多媒體卡規(guī)格 |
| 文件頁(yè)數(shù)： | 44/66頁(yè) |
| 文件大小： | 1422K |
| 代理商： | MC12U128NACA |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)當(dāng)前第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)
MultiMediaCard
TM
44
3 = stby
4 = tran
5 = data
6 = rcv
7 = prg
8 = dis
9–15 = reserved
‘0’ = not ready
‘1’ = ready
Permanently 0
‘0’ = disabled
‘1’ = enabled
8
EADY_FOR_DATA
SX
corresponds to buffer empty signaling on
the bus
A
7:6
5
reserved
APP_CMD
SR
The card will expect ACMD or indication
that the command has been interpreted
as ACMD.
C
4
3:2
1:0
4.9.8 Command Response Timings
All timing diagrams use the following schematics and abbreviations:
S
Start bit (= ‘0’)
T
Transmitter bit (Host = ‘1’, Card = ‘0’)
P
One-cycle pull-up (= ‘1’)
E
End bit (=1)
Z
High impedance state (-> = ‘1’)
D
Data bits
*
Repetition
CRC
Cyclic redundancy check bits (7 bits for command or
response, 16 bits for block data)
Card active
Host active
The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the card
respectively host output driver, while Z-bit is driven to (respectively kept) HIGH by the pull-up resistors
R
CMD
respectively R
DAT
. Actively driven P-bits are less sensitive to noise superposition.
Timing Values
Min
Max
NCR
2
64
NID
5
5
10*(TAAC*Fop+1
00*NSAC)
NRC
8
--
NCC
8
--
NWR
2
--
NST
2
2
The host command and the card response are clocked out with the rising edge of the host clock. The
delay between host command and card response is NCR clock cycles. The following timing diagram is
relevant for host command CMD3 :
reserved
reserved for application specific commands
reserved for manufacturer test mode
Permanently 0
Unit
Clock cycles
Clock cycles
NAC
2
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC56U064HACA | MultiMediaCard Specification |
| MC1GU064HACA | MultiMediaCard Specification |
| MC1GU032NACA | MultiMediaCard Specification |
| MC1GH128DACA-2SA00 | SAMSUNG MultiMediaCard |
| MC1GH128NACA-2SA00 | SAMSUNG MultiMediaCard |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC12U128NACA-0QC00 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:MultiMediaCard Specification |
| MC12U128NACB-0QC00 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:MultiMediaCard Specification |
| MC12U128NACC-0QC00 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:MultiMediaCard Specification |
| MC12U128NAFA-0QC00 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:MultiMediaCard Specification |
| MC12U128NAFB-0QC00 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:MultiMediaCard Specification |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。