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參數(shù)資料
| 型號： | MC14001UBCPG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC GATE NOR QUAD CMOS 14DIP |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 系列： | 4000B |
| 邏輯類型： | 或非門 |
| 電路數(shù)： | 4 |
| 輸入數(shù)： | 2 |
| 電源電壓： | 3 V ~ 18 V |
| 電流 - 靜態(tài)（最大值）： | 1µA |
| 輸出電流高，低： | 3.5mA，8.8mA |
| 邏輯電平 - 低： | 1 V ~ 2.5 V |
| 邏輯電平 - 高： | 4 V ~ 12.5 V |
| 額定電壓和最大 CL 時(shí)的最大傳播延遲： | 80ns @ 15V，50pF |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 通孔 |
| 供應(yīng)商設(shè)備封裝： | 14-PDIP |
| 封裝/外殼： | 14-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1124 (CN2011-ZH PDF) |
| 其它名稱： | MC14001UBCPGOS |
Semiconductor Components Industries, LLC, 2013
April, 2013 Rev. 9
1
Publication Order Number:
MC14001UB/D
MC14001UB, MC14011UB
UB-Suffix Series
CMOS Gates
The UB Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired. The UB set of
CMOS gates are inverting nonbuffered functions.
Features
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Linear and Oscillator Applications
Capable of Driving Two LowPower TTL Loads or One
LowPower Schottky TTL Load Over the Rated Temperature Range
Double Diode Protection on All Inputs
PinforPin Replacements for Corresponding CD4000 Series UB
Suffix Devices
These Devices are PbFree and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
55 to +125
°C
Tstg
Storage Temperature Range
65 to +150
°C
TL
Lead Temperature
(8Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
1
14
PDIP14
P SUFFIX
CASE 646
MC140xxUBCP
AWLYYWWG
SOIC14
D SUFFIX
CASE 751A
1
14
140xxUG
AWLYWW
http://onsemi.com
xx
= Specific Device Code
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G
= PbFree Package
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