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參數(shù)資料
| 型號(hào)： | MC14015BFELG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 0K |
| 描述： | IC SHIFT REGISTER DL 4B 16SOEIAJ |
| 產(chǎn)品變化通告： | 1Q2012 Discontinuation 30/Mar/2012 |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | 4000B |
| 邏輯類型： | 移位寄存器 |
| 輸出類型： | 標(biāo)準(zhǔn) |
| 元件數(shù)： | 2 |
| 每個(gè)元件的位元數(shù)： | 4 |
| 功能： | 串行至并行 |
| 電源電壓： | 3 V ~ 18 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOEIAJ |
| 包裝： | 帶卷 (TR) |
Semiconductor Components Industries, LLC, 2013
April, 2013 Rev. 8
1
Publication Order Number:
MC14015B/D
MC14015B
Dual 4-Bit Static
Shift Register
The MC14015B dual 4bit static shift register is constructed with
MOS PChannel and NChannel enhancement mode devices in a
single monolithic structure. It consists of two identical, independent
4state serialinput/paralleloutput registers. Each register has
independent Clock and Reset inputs with a single serial Data input.
The register states are type D masterslave flipflops. Data is shifted
from one stage to the next during the positivegoing clock transition.
Each register can be cleared when a high level is applied on the Reset
line. These complementary MOS shift registers find primary use in
buffer storage and serialtoparallel conversion where low power
dissipation and/or noise immunity is desired.
Features
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic EdgeClocked FlipFlop Design
Logic state is retained indefinitely with clock level either high or
low; information is transferred to the output only on the positive
going edge of the clock pulse
Capable of Driving Two Lowpower TTL Loads or One Lowpower
Schottky TTL Load Over the Rated Temperature Range
These Devices are PbFree and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation, per Package (Note 1)
500
mW
TA
Ambient Temperature Range
55 to +125
°C
Tstg
Storage Temperature Range
65 to +150
°C
TL
Lead Temperature
(8Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be
taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout
should be constrained to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
MARKING
DIAGRAMS
PDIP16
P SUFFIX
CASE 648
MC14015BCP
AWLYYWWG
SOIC16
D SUFFIX
CASE 751B
14015BG
AWLYWW
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G
= PbFree Indicator
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
16
1
16
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