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參數資料
型號: MC14024BDR2G
廠商: ON Semiconductor
文件頁數: 1/8頁
文件大小: 0K
描述: IC COUNTER RIPPLE 7STAGE 14SOIC
標準包裝: 1
系列: 4000B
邏輯類型: 二進制計數器
方向:
元件數: 1
每個元件的位元數: 7
復位: 異步
計數速率: 12MHz
觸發器類型: 正,負
電源電壓: 3 V ~ 18 V
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 14-SOICN
包裝: 標準包裝
其它名稱: MC14024BDR2GOSDKR
Semiconductor Components Industries, LLC, 2013
April, 2013 Rev. 9
1
Publication Order Number:
MC14024B/D
MC14024B
7-Stage Ripple Counter
The MC14024B is a 7stage ripple counter with short propagation
delays and high maximum clock rates. The Reset input has standard
noise immunity, however the Clock input has increased noise
immunity due to Hysteresis. The output of each counter stage is
buffered.
Features
Diode Protection on All Inputs
Output Transitions Occur on the Falling Edge of the Clock Pulse
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Lowpower TTL Loads or One Lowpower
Schottky TTL Load Over the Rated Temperature Range
PinforPin Replacement for CD4024B
These Devices are PbFree and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
55 to +125
°C
Tstg
Storage Temperature Range
65 to +150
°C
TL
Lead Temperature
(8Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
MARKING
DIAGRAMS
1
14
PDIP14
P SUFFIX
CASE 646
MC14024BCP
AWLYYWWG
SOIC14
D SUFFIX
CASE 751A
1
14
14024BG
AWLYWW
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G
= PbFree Package
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
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