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參數資料
| 型號： | MC14027BFL1 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 鎖存器 |
| 英文描述： | 4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | EIAJ, PLASTIC, SOIC-16 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 205K |
| 代理商： | MC14027BFL1 |
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14027B/D
MC14027B
Dual J-K Flip-Flop
The MC14027B dual J–K flip–flop has independent J, K, Clock (C),
Set (S) and Reset (R) inputs for each flip–flop. These devices may be
used in control, register, or toggle functions.
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Swing Independent of Fanout
Logic Edge–Clocked Flip–Flop Design —
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive–going
edge of the clock pulse
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Pin–for–Pin Replacement for CD4027B
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
– 0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
– 0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation,
per Package (Note 3.)
500
mW
TA
Ambient Temperature Range
– 55 to +125
°C
Tstg
Storage Temperature Range
– 65 to +150
°C
TL
Lead Temperature
(8–Second Soldering)
260
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
A
= Assembly Location
WL or L
= Wafer Lot
YY or Y
= Year
WW or W = Work Week
Device
Package
Shipping
ORDERING INFORMATION
MC14027BCP
PDIP–16
2000/Box
MC14027BD
SOIC–16
2400/Box
MC14027BDR2
SOIC–16
2500/Tape & Reel
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
1
16
PDIP–16
P SUFFIX
CASE 648
MC14027BCP
AWLYYWW
SOIC–16
D SUFFIX
CASE 751B
1
16
14027B
AWLYWW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14027B
AWLYWW
MC14027BF
SOEIAJ–16
See Note 1.
MC14027BFEL
SOEIAJ–16
See Note 1.
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