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參數資料
| 型號： | MC14042BF |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quad Transparent Latch |
| 中文描述： | 4000/14000/40000 SERIES, HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | EIAJ, SOIC-16 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 174K |
| 代理商： | MC14042BF |
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14042B/D
The MC14042B Quad Transparent Latch is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. Each latch has a separate data input, but all four
latches share a common clock. The clock polarity (high or low) used to
strobe data through the latches can be reversed using the polarity
input. Information present at the data input is transferred to outputs Q
and Q during the clock level which is determined by the polarity input.
When the polarity input is in the logic “0” state, data is transferred
during the low clock level, and when the polarity input is in the logic
“1” state the transfer occurs during the high clock level.
Buffered Data Inputs
Common Clock
Clock Polarity Control
Q and Q Outputs
Double Diode Input Protection
Supply Voltage Range = 3.0 Vdc to 1 8 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage Range
–0.5 to +18.0
V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V
DD
+ 0.5
V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
±
10
mA
P
D
Power Dissipation,
per Package (Note 3.)
500
mW
T
A
Ambient Temperature Range
–55 to +125
°
C
T
stg
Storage Temperature Range
–65 to +150
°
C
T
L
Lead Temperature
(8–Second Soldering)
260
°
C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
http://onsemi.com
A
WL or L
YY or Y
WW or W = Work Week
= Assembly Location
= Wafer Lot
= Year
Device
Package
Shipping
ORDERING INFORMATION
MC14042BCP
PDIP–16
2000/Box
MC14042BD
SOIC–16
2400/Box
MC14042BDR2
SOIC–16
2500/Tape & Reel
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
16
1
PDIP–16
P SUFFIX
CASE 648
MC14042BCP
AWLYYWW
SOIC–16
D SUFFIX
CASE 751B
1
16
14042B
AWLYWW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14042B
AWLYWW
MC14042BF
SOEIAJ–16
See Note 1.
MC14042BFEL
SOEIAJ–16
See Note 1.
MC14042BFR1
SOEIAJ–16
See Note 1.
MC14042BFR2
SOEIAJ–16
See Note 1.
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相關代理商/技術參數 |
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|---|---|
| MC14042BFEL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC14042BFR1 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Quad Transparent Latch |
| MC14042BFR2 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Quad Transparent Latch |
| MC14043B | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:CMOS MSI(Quad R-S Latches) |
| MC14043B_05 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:CMOS MSI Quad R−S Latches |
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