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參數資料
| 型號： | MC14042BFEL |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quad Transparent Latch |
| 中文描述： | 4000/14000/40000 SERIES, HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | EIAJ, PLASTIC, SOIC-16 |
| 文件頁數： | 4/8頁 |
| 文件大小： | 174K |
| 代理商： | MC14042BFEL |
MC14042B
http://onsemi.com
4
7. The formulas given are for the typical characteristics only at 25 C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
(7.)
(8.)
t
, t
= (0.55 ns/pF) C
+ 9.5 ns
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
TLH
THL
L
15
15
15
10
15
t
THL
15
—
—
80
50
40
5.0
—
60
60
40
25
20
—
40
120
120
—
—
—
100
80
200
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 35 ns
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 135 ns
t
PHL
5.0
—
220
440
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 35 ns
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 135 ns
t
PLH
,
t
PHL
5.0
—
220
440
ns
Clock Pulse Width
t
WH
ns
Clock Pulse Rise and Fall Time
t
TLH
,
THL
15
—
—
4.0
s
Hold Time
10
15
t
h
30
25
0
0
—
—
ns
Setup Time
t
su
ns
Figure 1. AC and Power Dissipation Test Circuit and Timing Diagram
(Data to Output)
V
DD
V
SS
PULSE
GENERATOR 1
16
5
6
4
7
13
14
CLOCK
POLARITY
D0
D1
D2
D3
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
15
1
12
11
9
10
3
2
8
For Power Dissipation test, each output
is loaded with capacitance C
L
.
1
f
20 ns
20 ns
DATA INPUT
Q OUTPUT
Q OUTPUT
t
PLH
t
PHL
t
TLH
t
THL
t
TLH
t
THL
90%
50%
10%
50%
90%
10%
90%
10%
50%
t
PHL
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