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參數(shù)資料
| 型號： | MC14043B |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | Replaced by TPS2300 : 2.75-13.6V Dual Sequencing HotSwap IC 16-SOIC -40 to 85 |
| 中文描述： | 微星的CMOS（四恏巴鎖存） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 192K |
| 代理商： | MC14043B |
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14043B/D
Quad R–S Latches
The MC14043B and MC14044B quad R–S latches are constructed
with MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. Each latch has an independent Q output
and set and reset inputs. The Q outputs are gated through three–state
buffers having a common enable input. The outputs are enabled with a
logical “1” or high on the enable input; a logical “0” or low
disconnects the latch from the Q outputs, resulting in an open circuit at
the Q outputs.
Double Diode Input Protection
Three–State Outputs with Common Enable
Outputs Capable of Driving Two Low–power TTL Loads or One
Low–Power Schottky TTL Load Over the Rated Temperature Range
Supply Voltage Range = 3.0 Vdc to 18 Vdc
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage Range
–0.5 to +18.0
V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V
DD
+ 0.5
V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
±
10
mA
P
D
Power Dissipation,
per Package (Note 3.)
500
mW
T
A
Ambient Temperature Range
–55 to +125
°
C
T
stg
Storage Temperature Range
–65 to +150
°
C
T
L
Lead Temperature
(8–Second Soldering)
260
°
C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
http://onsemi.com
XX
A
WL or L
YY or Y
WW or W = Work Week
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
Device
Package
Shipping
ORDERING INFORMATION
MC14043BCP
PDIP–16
2000/Box
MC14043BD
SOIC–16
2400/Box
MC14043BDR2
SOIC–16
2500/Tape & Reel
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
16
1
PDIP–16
P SUFFIX
CASE 648
MC140XXBCP
AWLYYWW
SOIC–16
D SUFFIX
CASE 751B
1
16
140XXB
AWLYWW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC140XXB
AWLYWW
MC14043BF
SOEIAJ–16
See Note 1.
MC14043BFEL
SOEIAJ–16
See Note 1.
MC14044BCP
PDIP–16
2000/Box
MC14044BD
SOIC–16
2400/Box
MC14044BDR2
SOIC–16
2500/Tape & Reel
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC14043BDR2 | Replaced by TPS2300 : 2.75-13.6V Dual Sequencing HotSwap IC 16-SOIC -40 to 85 |
| MC14043BF | CMOS MSI(Quad R-S Latches) |
| MC14043BFEL | CMOS MSI(Quad R-S Latches) |
| MC14044BCP | CMOS MSI(Quad R-S Latches) |
| MC14044BD | CMOS MSI(Quad R-S Latches) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC14043B_05 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:CMOS MSI Quad R−S Latches |
| MC14043BALR | 制造商:Freescale Semiconductor 功能描述: |
| MC14043BBEBS | 制造商:Motorola Inc 功能描述: |
| MC14043BCL | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:CMOS MSI Quad R-S Latches |
| MC14043BCP | 功能描述:閉鎖 3-18V Quad R-S RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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