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參數(shù)資料
型號(hào): MC14094BDT
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: 8-Stage Shift/Store Register with Three-State Outputs
中文描述: 4000/14000/40000 SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16
封裝: TSSOP-16
文件頁數(shù): 1/6頁
文件大小: 232K
代理商: MC14094BDT
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
1
MC14094B
The MC14094B combines an 8–stage shift register with a data latch for
each stage and a three–state output from each latch.
Data is shifted on the positive clock transition and is shifted from the
seventh stage to two serial outputs. The QS output data is for use in
high–speed cascaded systems. The Q
S output data is shifted on the
following negative clock transition for use in low–speed cascaded systems.
Data from each stage of the shift register is latched on the negative
transition of the strobe input. Data propagates through the latch while strobe
is high.
Outputs of the eight data latches are controlled by three–state buffers
which are placed in the high–impedance state by a logic Low on Output
Enable.
Three–State Outputs
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
Input Diode Protection
Data Latch
Dual Outputs for Data Out on Both Positive and Negative Clock
Transitions
Pin–for–Pin Compatible with CD4094B
MAXIMUM RATINGS*
Symbol
Parameter
VDD
DC Supply Voltage
Vin, Vout
Input or Output Voltage (DC or Transient)
Iin, Iout
Input or Output Current (DC or Transient),
Value
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
±
10
Unit
V
V
mA
Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
Clock
Enable
Strobe
Data
Parallel Outputs
Serial Outputs
Output
Q1
QN
Z
QS*
Q7
Q
S
0
X
X
Z
No Chg.
0
X
X
Z
Z
No Chg.
Q7
1
0
X
No Chg.
No Chg.
Q7
No Chg.
1
1
0
0
QN–1
QN–1
No Chg.
Q7
No Chg.
1
1
1
1
Q7
No Chg.
1
1
1
No Chg.
No Chg.
Q7
Z = High Impedance
* At the positive clock edge, information in the 7th shift register stage is transferred to
Q8 and QS.
X = Don’t Care
SEMICONDUCTOR TECHNICAL DATA
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
TA = – 55
°
to 125
°
C for all packages.
Plastic
Ceramic
SOIC
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
Q7
Q6
Q5
OUTPUT
ENABLE
VDD
QS
Q
S
Q8
Q1
CLOCK
DATA
STROBE
VSS
Q4
Q3
Q2
PIN ASSIGNMENT
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
VDD.
相關(guān)PDF資料
PDF描述
MC14094BDTR2 8-Stage Shift/Store Register with Three-State Outputs
MC14094BF 8-Stage Shift/Store Register with Three-State Outputs
MC14094BCP 8-Stage Shift/Store Register with Three-State Outputs
MC14094BD 8-Stage Shift/Store Register with Three-State Outputs
MC14097BCP Analog Multiplexers/Demultiplexers
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