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參數資料
| 型號： | MC14099BFELG |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 鎖存器 |
| 英文描述： | 4000/14000/40000 SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16 |
| 封裝： | EIAJ, PLASTIC, SOIC-16 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 101K |
| 代理商： | MC14099BFELG |
Semiconductor Components Industries, LLC, 2005
August, 2005 Rev. 6
1
Publication Order Number:
MC14099B/D
MC14099B
8Bit Addressable Latches
The MC14099B is an 8bit addressable latch. Data is entered in
serial form when the appropriate latch is addressed (via address pins
A0, A1, A2) and write disable is in the low state. For the MC14099B
the input is a unidirectional write only port.
The data is presented in parallel at the output of the eight latches
independently of the state of Write Disable, Write/Read or Chip
Enable.
A Master Reset capability is available on both parts.
Features
Serial Data Input
Parallel Output
Master Reset
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Lowpower TTL Loads or One LowPower
Schottky TTL Load over the Rated Temperature Range
MC14099B pin for pin compatible with CD4099B
PbFree Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
55 to +125
°C
Tstg
Storage Temperature Range
65 to +150
°C
TL
Lead Temperature
(8Second Soldering)
260
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING
DIAGRAMS
PDIP16
P SUFFIX
CASE 648
MC14099BCP
AWLYYWWG
SOIC16
DW SUFFIX
CASE 751G
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
G
= PbFree Indicator
SOEIAJ16
F SUFFIX
CASE 966
MC14099B
ALYWG
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
16
1
16
14099BG
AWLYYWW
16
1
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