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參數(shù)資料
| 型號(hào)： | MC14415VP |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 標(biāo)準(zhǔn)邏輯 |
| 英文描述： | Digital Signal Processors 68-LCCC -55 to 125 |
| 中文描述： | SPECIALTY LOGIC CIRCUIT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大小： | 253K |
| 代理商： | MC14415VP |
MOTOROLA CMOS LOGIC DATA
MC14415
290
MC14415 quad timer/driver is constructed with complementary MOS
enhancement mode devices. The output pulse width of each digital timer is
a function of the input clock frequency. Once the proper input sequence is
detected the output buffer is set (turned on), and after 100 clock pulses are
counted, the output buffer is reset (turned off).
The MC14415 was designed specifically for application in high speed line
printers to provide the critical timing of the hammer drivers, but may be used
in many applications requiring precision pulse widths.
Four Precision Digital Time Delays
Schmitt Trigger Clock Conditioning
NPN Bipolar Output Drivers
Timing Disable Capability Using Inhibit Output
Positive or Negative Edge Strobing on the Inputs
(Voltages Referenced to VSS)
Rating
DC Supply Voltage MC14415FL, FP,DW
Symbol
VDD
Value
– 0.5 to + 18.0
Unit
V
Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
BLOCK DIAGRAM
OUTPUT INHIBIT 15
11 OUTPUT D
CLOCK
1
OUTPUT SET
2
INPUT DISABLE 10
STROBE 1
7
STROBE 2
9
SET D
6
SET C
5
SET B
4
SET A
3
12 OUTPUT C
13 OUTPUT B
14 OUTPUT A
VDD = PIN 16
VSS = PIN 8
INPUT
LOGIC
DIVIDE–BY–
100
COUNTERS
OUTPUT
BUFFERS
COMMON
LOGIC
CLOCK
CONDITIONING
CIRCUIT
SEMICONDUCTOR TECHNICAL DATA
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14415FP (3.0 V–18 V)
MC14415VP (3.0 V–6.0 V)
MC14415FL (3.0 V–18 V)
MC14415VL (3.0 V–6.0 V)
MC14415DW (3.0 V–18 V)
Plastic
Plastic
Ceramic
Ceramic
SOIC
TA = – 55
°
to 125
°
C for all packages.
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
OUT C
OUT B
OUT A
VDD
INH
ST2
DIS
OUT D
SET B
SET A
SET
CLOCK
VSS
ST 1
SET D
SET C
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