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參數資料
| 型號： | MC14506UBCL |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual 2-Wide, 2-Input Expandable AND-OR-INVERT Gate |
| 中文描述： | 4000/14000/40000 SERIES, DUAL 4-INPUT AND-OR-INVERT GATE, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 238K |
| 代理商： | MC14506UBCL |
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
1
MC14506UB
# !#"
$!
"
The MC14506UB is an expandable AND–OR–INVERT gate with inhibit
and 3–state output. The expand option allows cascading with any other gate,
which may be carried as far as desired as long as the propagation delay
added with each gate is considered. For example, the second AOI gate in
this device may be used to expand the first gate, giving an expanded 4–wide,
2–input AOI gate. This device is useful in data control and digital multiplexing
applications.
3–State Output
Separate Inhibit Line
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Schottky TTL Load Over the Rated Temperature Range
VDD
Vin, Vout
Iin, Iout
DC Supply Voltage
– 0.5 to + 18.0
V
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
±
10
V
Input or Output Current (DC or Transient),
per Pin
mA
PD
Tstg
TL
Power Dissipation, per Package
500
mW
Storage Temperature
– 65 to + 150
C
Lead Temperature (8–Second Soldering)
260
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
LOGIC DIAGRAM
AA
BA
CA
DA
EA
1
2
3
4
5
INH
6
DIS 14
EB13
DB12
CB11
BB10
AB
9
3–STATE
OUTPUT DISABLE
15 ZA
7
ZB
VDD = PIN 16
VSS = PIN 8
Z = (AB + CD + E + I)
SEMICONDUCTOR TECHNICAL DATA
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXUBCP
MC14XXXUBCL
MC14XXXUBD
TA = – 55
°
to 125
°
C for all packages.
Plastic
Ceramic
SOIC
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
VDD.
TRUTH TABLE
Inhibit
A B C D E
Disable
Z
0
0 X 0 X 1
0 X X 0
X 0
0 X 1
X 0 X 0
1
1 X X X
X X 1
X X X X 0
X X X X X
X X X X X
0
0
0
1
0
0
0
0
0
X
X
X
1
X
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1 X
High
Impedance
X = Don’t Care
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