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參數(shù)資料
| 型號： | MC14521BF |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 諧振器 |
| 英文描述： | 24-Stage Frequency Divider |
| 中文描述： | 4000/14000/40000 SERIES, PRESCALER, PDSO16 |
| 封裝： | EIAJ, SOIC-16 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 219K |
| 代理商： | MC14521BF |
MC14521B
http://onsemi.com
7
Reset
In 2
Out 2
V
SS
′
V
DD
′
Q18 thru
Q24
Counter is in three 8–stage
sections in parallel mode
Counter is reset. In 2 and
Out 2 are connected
together
1
0
0
V
DD
Gnd
0
A test function (see Figure 8) has been
included for the reduction of test time required to
exercise all 24 counter stages. This test function
divides the counter into three 8–stage sections,
and 255 counts are loaded in each of the
8–stage sections in parallel. All flip–flops are
now at a logic “1”. The counter is now returned
to the normal 24–stages in series configuration.
One more pulse is entered into Input 2 (In 2)
which will cause the counter to ripple from an all
“1” state to an all “0” state.
0
1
1
First “0” to “1” transition
on In 2, Out 2 node.
255 “0” to “1” transitions
are clocked into this In 2,
Out 2 node.
0
1
—
—
—
0
1
—
—
—
1
1
1
The 255th “0” to “1”
transition.
0
0
0
0
G d
Gnd
1
1
1
0
V
DD
1
Counter converted back to
24–stages in series mode.
Out 2 converts back to an
output.
Counter ripples from an all
“1” state to an all “0” stage.
1
0
1
0
1
0
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