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參數資料
型號: MC14531BCL
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: 12-Bit Parity Tree
中文描述: 4000/14000/40000 SERIES, 12-BIT PARITY GENERATOR/CHECKER, CONFIGURABLE OUTPUT, CDIP16
封裝: CERAMIC, DIP-16
文件頁數: 1/5頁
文件大小: 172K
代理商: MC14531BCL
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
1
MC14531B
The MC14531B 12–bit parity tree is constructed with MOS P–channel and
N–channel enhancement mode devices in a single monolithic structure. The
circuit consists of 12 data–bit inputs (D0 thru D11), and even or odd parity
selection input (W) and an output (Q). The parity selection input can be
considered as an additional bit. Words of less than 13 bits can generate an
even or odd parity output if the remaining inputs are selected to contain an
even or odd number of ones, respectively. Words of greater than 12–bits can
be accommodated by cascading other MC14531B devices by using the W
input. Applications include checking or including a redundant (parity) bit to a
word for error detection/correction systems, controller for remote digital
sensors or switches (digital event detection/correction), or as a multiple input
summer without carries.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
Diode Protection on All Inputs
MAXIMUM RATINGS*
Symbol
Parameter
VDD
DC Supply Voltage
Value
– 0.5 to + 18.0
Unit
V
TL
* Maximum Ratings are those values beyond which damage to the device may occur.
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
Storage Temperature
– 65 to + 150
C
Lead Temperature (8–Second Soldering)
260
C
LOGIC DIAGRAM
Q = D0
D1
D2
D11
W
VDD = PIN 16
VSS = PIN 8
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
ODD/EVEN W
9 Q
7
6
5
4
3
2
1
15
14
13
12
11
10
SEMICONDUCTOR TECHNICAL DATA
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
TA = – 55
°
to 125
°
C for all packages.
Plastic
Ceramic
SOIC
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
TRUTH TABLE
Inputs
Output
Decimal
(Octal)
Equivalent
W
D11
D10
D2
D1
D0
Q*
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
2
3
(0)
(1)
(2)
(3)
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
4
5
6
7
(4)
(5)
(6)
(7)
1
0
0
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
1
1
1
1
1
1
1
1.
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
8184 (17770)
8185 (17771)
8186 (17772)
8187 (17773)
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
8188 (17774)
8189 (17775)
8190 (17776)
8191 (17777)
1
0
0
1
*0 = Even Parity
NOTE:May redefine to suit application by manipulating W and/or other
available D’s.
1 = Odd Parity
相關PDF資料
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