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參數資料
| 型號： | MC14543BFL1 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 編、解碼器及復用、解復用 |
| 英文描述： | 4000/14000/40000 SERIES, SEVEN SEGMENT DECODER/DRIVER, CONFIGURABLE OUTPUT, PDSO16 |
| 封裝： | EIAJ, PLASTIC, SOIC-16 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 234K |
| 代理商： | MC14543BFL1 |
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14543B/D
MC14543B
BCD-to-Seven Segment
Latch/Decoder/Driver for
Liquid Crystals
The MC14543B BCD–to–seven segment latch/decoder/driver is
designed for use with liquid crystal readouts, and is constructed with
complementary MOS (CMOS) enhancement mode devices. The
circuit provides the functions of a 4–bit storage latch and an 8421
BCD–to–seven segment decoder and driver. The device has the
capability to invert the logic levels of the output combination. The
phase (Ph), blanking (BI), and latch disable (LD) inputs are used to
reverse the truth table phase, blank the display, and store a BCD code,
respectively. For liquid crystal (LC) readouts, a square wave is applied
to the Ph input of the circuit and the electrically common backplane of
the display. The outputs of the circuit are connected directly to the
segments of the LC readout. For other types of readouts, such as
light–emitting diode (LED), incandescent, gas discharge, and
fluorescent readouts, connection diagrams are given on this data sheet.
Applications include instrument (e.g., counter, DVM etc.) display
driver, computer/calculator display driver, cockpit display driver, and
various clock, watch, and timer uses.
Latch Storage of Code
Blanking Input
Readout Blanking on All Illegal Input Combinations
Direct LED (Common Anode or Cathode) Driving Capability
Supply Voltage Range = 3.0 V to 18 V
Capable of Driving 2 Low–power TTL Loads, 1 Low–power Schottky
TTL Load or 2 HTL Loads Over the Rated Temperature Range
Pin–for–Pin Replacement for CD4056A (with Pin 7 Tied to V
SS).
Chip Complexity: 207 FETs or 52 Equivalent Gates
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
– 0.5 to +18.0
V
Vin
Input Voltage Range, All Inputs
– 0.5 to VDD + 0.5
V
Iin
DC Input Current per Pin
±10
mA
PD
Power Dissipation,
per Package (Note 3.)
500
mW
TA
Operating Temperature Range
– 55 to +125
°C
Tstg
Storage Temperature Range
– 65 to +150
°C
IOHmax
IOLmax
Maximum Continuous Output
Drive Current (Source or Sink)
10
(per Output)
mA
POHmax
POLmax
Maximum Continuous Output
Power (Source or Sink) (4.)
70
(per Output)
mW
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_C From 65_C To 125_C
4. POHmax = IOH (VOH – VDD) and POLmax = IOL (VOL – VSS)
http://onsemi.com
A
= Assembly Location
WL or L
= Wafer Lot
YY or Y
= Year
WW or W = Work Week
Device
Package
Shipping
ORDERING INFORMATION
MC14543BCP
PDIP–16
2000/Box
MC14543BD
SOIC–16
48/Rail
MC14543BDR2
SOIC–16
2500/Tape & Reel
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
1
16
PDIP–16
P SUFFIX
CASE 648
MC14543BCP
AWLYYWW
SOIC–16
D SUFFIX
CASE 751B
1
16
14543B
AWLYWW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14543B
AWLYWW
MC14543BFEL
SOEIAJ–16
See Note 1.
MC14543BF
SOEIAJ–16
See Note 1.
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid ap-
plications of any voltage higher than maximum rated
voltages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained to the
range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either VSS or VDD). Unused out-
puts must be left open.
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