
MOTOROLA CMOS LOGIC DATA
1
MC14553B
3-Digit BCD Counter
The MC14553B 3–digit BCD counter consists of 3 negative edge triggered
BCD counters that are cascaded synchronously. A quad latch at the output
of each counter permits storage of any given count. The information is then
time division multiplexed, providing one BCD number or digit at a time. Digit
select outputs provide display control. All outputs are TTL compatible.
An on–chip oscillator provides the low–frequency scanning clock which
drives the multiplexer output selector.
This device is used in instrumentation counters, clock displays, digital
panel meters, and as a building block for general logic applications.
TTL Compatible Outputs
On–Chip Oscillator
Cascadable
Clock Disable Input
Pulse Shaping Permits Very Slow Rise Times on Input Clock
Output Latches
Master Reset
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage
– 0.5 to + 18.0
V
Vin, Vout Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
Iin
Input Current (DC or Transient), per Pin
± 10
mA
Iout
Output Current (DC or Transient), per Pin
+ 20
mA
PD
Power Dissipation, per Package
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
TL
Lead Temperature (8–Second Soldering)
260
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/
_C From 100_C To 125_C
TRUTH TABLE
Inputs
Outputs
Master
Reset
Clock
Disable
LE
Outputs
0
No Change
0
Advance
0
X
1
X
No Change
0
1
0
Advance
0
1
0
No Change
0
X
No Change
0
X
Latched
0
X
1
Latched
1
X
0
Q0 = Q1 = Q2 = Q3 = 0
X = Don’t Care
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
MC14553B
BLOCK DIAGRAM
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP
Plastic
MC14XXXBCL
Ceramic
MC14XXXBDW
SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
12
10
11
13
9
7
6
5
14
2
1
15
VDD = PIN 16
VSS = PIN 8
4
3
CLOCK
LE
DIS
MR
Q0
Q1
Q2
Q3
O.F.
DS1
DS2
DS3
CIA
CIB