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參數資料
| 型號： | MC14C89ABP |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | OC-48,24,12 SONET SDH Multi-rate Transceiver 100-HTQFP -40 to 85 |
| 中文描述： | LINE RECEIVER, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁數： | 1/6頁 |
| 文件大小： | 118K |
| 代理商： | MC14C89ABP |
Device
Operating
Temperature Range
Package
SEMICONDUCTOR
TECHNICAL DATA
QUAD LOW POWER
LINE RECEIVERS
ORDERING INFORMATION
MC14C89BP
TA = – 40
°
to +85
°
C
Plastic DIP
Order this document by MC14C89B/D
PIN CONNECTIONS
P SUFFIX
PLASTIC PACKAGE
CASE 646
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO–14)
(Top View)
Ground
9
10
11
12
14
13
7
6
5
4
3
1
2
8
Output A
Input A
Input B
Output B
Input D
VCC
Output D
Output C
Response
Control D
Input C
Response
Control C
Response
Control B
Response
Control A
MC14C89ABP
Plastic DIP
MC14C89ABD
SO–14
1
MOTOROLA ANALOG IC DEVICE DATA
The MC14C89B and MC14C89AB are low monolithic quad line receivers
using bipolar technology, which conform to the EIA–232–E, EIA–562 and
CCITT V.28 Recommendations. The outputs feature LSTTL and CMOS
compatibility for easy interface to +5.0 V digital systems. Internal
time–domain filtering eliminates the need for external filter capacitors in most
cases.
The MC14C89B has an input hysteresis of 0.35 V, while the MC14C89AB
hysteresis is 0.95 V. The response control pins allow adjustment of the
threshold level if desired. Additionally, an external capacitor may be added
for additional noise filtering.
The MC14C89B and MC14C89AB are available in both a 14 pin
dual–in–line plastic DIP and SOIC package.
Features:
Low Power Consumption
Meets EIA–232–E, EIA–562, and CCITT V.28 Recommendations
TTL/CMOS Compatible Outputs
Standard Power Supply: + 5.0 V
±
10%
Pin Equivalent to MC1489, MC1489A, TI’s SN75C189/A, SN75189/A
and National Semiconductor’s DS14C89/A
External Filtering Not Required in Most Cases
Threshold Level Externally Adjustable
Hysteresis: 0.35 V for MC14C89B, 0.95 V for MC14C89AB
Available in Plastic DIP, and Surface Mount Packaging
Operating Ambient Temperature: –40
°
to +85
°
C
Representative Block Diagram
(Each Receiver)
Input
VCC
Output
Response
Control
Motorola, Inc. 1996
Rev 0
相關PDF資料 |
PDF描述 |
|---|---|
| MC14C89B | QUAD LOW POWER LINE RECEIVERS |
| MC14C89BP | QUAD LOW POWER LINE RECEIVERS |
| MC14C89 | QUAD LOW POWER LINE RECEIVERS |
| MC14C89ABD | QUAD LOW POWER LINE RECEIVERS |
| MC14C89ABP | OC-48,24,12 SONET SDH Multi-rate Transceiver 100-HTQFP -40 to 85 |
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