- 您現在的位置：買賣IC網 > PDF目錄382300 > MC1DU512HACA (SAMSUNG SEMICONDUCTOR CO. LTD.) Film Capacitor; Capacitor Type:Motor Start/Motor Run; Voltage Rating:370VAC; Capacitor Dielectric Material:Polypropylene; Capacitance:4uF; Capacitance Tolerance:+/- 10%; Lead Pitch:20.64mm; Package/Case:32; Series:MPF PDF資料下載
參數資料
| 型號： | MC1DU512HACA |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Film Capacitor; Capacitor Type:Motor Start/Motor Run; Voltage Rating:370VAC; Capacitor Dielectric Material:Polypropylene; Capacitance:4uF; Capacitance Tolerance:+/- 10%; Lead Pitch:20.64mm; Package/Case:32; Series:MPF |
| 中文描述： | 多媒體卡規格 |
| 文件頁數： | 44/66頁 |
| 文件大小： | 1422K |
| 代理商： | MC1DU512HACA |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁當前第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
MultiMediaCard
TM
44
3 = stby
4 = tran
5 = data
6 = rcv
7 = prg
8 = dis
9–15 = reserved
‘0’ = not ready
‘1’ = ready
Permanently 0
‘0’ = disabled
‘1’ = enabled
8
EADY_FOR_DATA
SX
corresponds to buffer empty signaling on
the bus
A
7:6
5
reserved
APP_CMD
SR
The card will expect ACMD or indication
that the command has been interpreted
as ACMD.
C
4
3:2
1:0
4.9.8 Command Response Timings
All timing diagrams use the following schematics and abbreviations:
S
Start bit (= ‘0’)
T
Transmitter bit (Host = ‘1’, Card = ‘0’)
P
One-cycle pull-up (= ‘1’)
E
End bit (=1)
Z
High impedance state (-> = ‘1’)
D
Data bits
*
Repetition
CRC
Cyclic redundancy check bits (7 bits for command or
response, 16 bits for block data)
Card active
Host active
The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the card
respectively host output driver, while Z-bit is driven to (respectively kept) HIGH by the pull-up resistors
R
CMD
respectively R
DAT
. Actively driven P-bits are less sensitive to noise superposition.
Timing Values
Min
Max
NCR
2
64
NID
5
5
10*(TAAC*Fop+1
00*NSAC)
NRC
8
--
NCC
8
--
NWR
2
--
NST
2
2
The host command and the card response are clocked out with the rising edge of the host clock. The
delay between host command and card response is NCR clock cycles. The following timing diagram is
relevant for host command CMD3 :
reserved
reserved for application specific commands
reserved for manufacturer test mode
Permanently 0
Unit
Clock cycles
Clock cycles
NAC
2
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
相關PDF資料 |
PDF描述 |
|---|---|
| MC12U128HACA | MultiMediaCard Specification |
| MC12U128NACA | MultiMediaCard Specification |
| MC56U064HACA | MultiMediaCard Specification |
| MC1GU064HACA | MultiMediaCard Specification |
| MC1GU032NACA | MultiMediaCard Specification |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MC1DU512HACA-0QC00 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:MultiMediaCard Specification |
| MC1DU512HACB-0QC00 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:MultiMediaCard Specification |
| MC1DU512HACC-0QC00 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:MultiMediaCard Specification |
| MC1DU512HAFA-0QC00 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:MultiMediaCard Specification |
| MC1DU512HAFB-0QC00 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:MultiMediaCard Specification |
發布緊急采購，3分鐘左右您將得到回復。