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參數(shù)資料
| 型號： | MC1GH128NACA-2SA00 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | SAMSUNG MultiMediaCard |
| 中文描述： | 三星多媒體 |
| 文件頁數(shù)： | 72/102頁 |
| 文件大?。?/td> | 1384K |
| 代理商： | MC1GH128NACA-2SA00 |
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MultiMediaCard
TM
72
Sep.22.2005
Revision 0.3
6.12 Timing Diagrams
All timing diagrams use the following schematics and abbreviations:
The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the card respectively host output
driver, while Z-bit is driven to (respectively kept) HIGH by the pull-up resistors R
CMD
respectively R
DAT
. Actively-driven P-
bits are less sensitive to noise.
All timing values are defined in Table 6-25.
6.12.1 Command and Response
Both host command and card response are clocked out with the rising edge of the host clock.
Card identification and card operation conditions timing
The card identification (CMD2) and card operation conditions (CMD1) timing are processed in the open-drain mode. The
card response to the host command starts after exactly N
ID
clock cycles.
Figure 6-7 : Identification Timing (Card Identification Mode)
Assign a card relative address
The SET_RCA (CMD 3) is also processed in the open-drain mode. The minimum delay between the host command and
card response is N
CR
clock cycles.
Figure 6-8 : SET_RCA Timing (Card Identification Mode)
Symbol
Definition
S
Start bit (= ‘0’)
T
Transmitter bit (Host = ‘1’, Card = ‘0’)
P
One-cycle pull-up (= ‘1’)
E
End bit (=’1’)
Z
High impedance state (-> = ‘1’)
X
Driven value, ‘1’ or ‘0’
D
Data bits
*
Repetition
CRC
Cyclic redundancy check bits (7 bits)
Card active
Host active
Table 6-24 : Timing Diagram Symbols
←
Host Command
→ ←
N
ID
cycles
→
S T
content
CRC E Z
←
CID or OCR
→
content
CMD
* * *
Z S T
Z Z Z
←
Host Command
→
←
N
CR
cycles
→
←
S T
content
CRC E Z
Response
content
→
CRC E Z Z Z
CMD
* * *
Z S T
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| MC1GU016HACC-0QC00 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:MultiMediaCard Specification |
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