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參數資料
| 型號： | MC1GU256NACA |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | MultiMediaCard Specification |
| 中文描述： | 多媒體卡規格 |
| 文件頁數： | 60/66頁 |
| 文件大小： | 1422K |
| 代理商： | MC1GU256NACA |
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MultiMediaCard
TM
60
Figure 4-13 Data Error Token
The 4 least significant bits (LSB) are the same error bits as in the response format R2.
4.10.15 Clearing Status Bits
As described in the previous paragraphs, in SPI mode, status bits are reported to the host in three
different formats : response R1, response R2 and data error token (the same bits may exist in multiple
response types – e.g. Card ECC failed)
As in the MultiMediaCard mode, error bits are cleared when read by the host, regardless of the
response format. State indicators are either cleared by reading or in accordance with the card state. All
Error/Status bits defined in MultiMediaCard mode, with the exception of the underrun and overrun,
have the same meaning and usage in SPI mode. The following table summarizes the set and clear
conditions for the various status bits :
- Type:
E: Error bit.
S: Status bit.
R: Detected and set for the actual command response.
X: Detected and set during command execution. The host must poll the card by sending status
Command in order to read these bits.
- Clear Condition:
A : According to the card state.
C: Clear by read.
SPI Mode Status Bits
Identifier
Included in
resp
Type
Value
Description
Clear
conditi
on
C
Out of Range
R2
DataErr
E R X
‘0’ = no error
‘1’ = error
The commands argument was
out of allowed range for this
card.
A address which did not match
the block length was used in the
command.
An error in the sequence of
erase command sequence.
Address Error
R1 R2
E R X
‘0’ = no error
‘1’ = error
C
Erase
Sequence
Error
Error Param
R1 R2
E R
‘0’ = no error
‘1’ = error
C
R2
E X
‘0’ = no error
‘1’ = error
‘0’ = no error
‘1’ = error
‘0’ = not
protected
‘1’ = protected
‘0’ = no error
An error in the parameters of
erase commands occurred.
An error in the parameters of the
command.
Attemp to program a write
protected block.
C
Parameter
Error
WP Violation
R1 R2
E R X
C
R2
E R X
C
Com CRC
R1 R2
E R
The CRC check of the previous
C
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