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參數(shù)資料
型號: MC2GH256NMCA-2SA00
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: SAMSUNG MultiMediaCard
中文描述: 三星多媒體
文件頁數(shù): 67/102頁
文件大小: 1384K
代理商: MC2GH256NMCA-2SA00
MultiMediaCard
TM
67
Sep.22.2005
Revision 0.3
There are five types of responses. Their formats are defined as follows:
R1
(normal response command): code length 48 bit. The bits 45:40 indicate the index of the command to be responded
to, this value being interpreted as a binary coded number (between 0 and 63). The status of the card is coded in 32 bits.
The card status is described in Chapter
R1b
is identical to R1 with an optional busy signal transmitted on the data line DAT0. The card may become busy after
receiving these commands based on its state prior to the command reception. Refer to Section for detailed description
and timing diagrams.
R2
(CID, CSD
register): code length 136 bits. The contents of the CID register are sent as a response to the commands
CMD2 and CMD10. The contents of the CSD register are sent as a response to CMD9. Only
the bits [127...1] of the CID
and CSD are transferred, the reserved bit [0] of these registers is replaced by the end bit of the response.
R3
(OCR
register): code length 48 bits. The contents of the OCR register is sent as a response to CMD1. The
level cod-
ing
is as follows: restricted voltage windows=LOW, card busy=LOW.
R4 and R5 : responses are not supported.
Bit position
Width (bits)
Value
Description
47
1
‘0’
46
1
‘0’
[45:40]
6
x
[39:8]
32
x
card status
[7:1]
7
x
CRC7
0
1
‘1’
start bit
transmission bit
command index
Table 6-19 : Response R1
end bit
Bit position
Width (bits)
Value
Description
135
1
‘0’
start bit
134
1
‘0’
[133:128]
6
‘111111’
check bits
[127:1]
127
x
0
1
‘1’
transmission bit
CID or CSD register incl. inter-
nal CRC7
end bit
Bit position
Width (bits)
Value
Description
47
1
‘0’
46
1
‘0’
[45:40]
6
‘111111’
check bits
[39:8]
32
x
[7:1]
7
‘1111111’
check bits
0
1
‘1’
start bit
transmission bit
OCR register
end bit
Table 6-20 : Response R2
Table 6-21 : Response R3
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