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參數資料
| 型號： | MC3100EP35DTG |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | 3.3V / 5V ECL JK Flip−Flop |
| 文件頁數： | 1/11頁 |
| 文件大小： | 164K |
| 代理商： | MC3100EP35DTG |
Semiconductor Components Industries, LLC, 2006
December, 2006
Rev. 5
1
Publication Order Number:
MC10EP35/D
MC10EP35, MC100EP35
3.3V / 5VECL JK FlipFlop
Description
The MC10/100EP35 is a higher speed/low voltage version of the
EL35 JK flip
flop. The J/K data enters the master portion of the
flip
flop when the clock is LOW and is transferred to the slave, and
thus the outputs, upon a positive transition of the clock. The reset pin is
asynchronous and is activated with a logic HIGH.
The 100 Series contains temperature compensation.
Features
410 ps Propagation Delay
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: V
CC
= 3.0 V to 5.5 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
3.0 V to
5.5 V
Open Input Default State
Q Output Will Default LOW with Inputs Open or at V
EE
Pb
Free Packages are Available
*For additional marking information, refer to
Application Note AND8002/D.
H
K
5R
3M
= MC10
= MC100
= MC10
= MC100
A
L
Y
W
M
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb
Free Package
ALYW
HP35
ALYW
KP35
MARKING
DIAGRAMS*
SOIC
8
D SUFFIX
CASE 751
TSSOP
8
DT SUFFIX
CASE 948R
1
8
1
8
1
8
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
1
8
HEP35
ALYW
1
8
KEP35
ALYW
1
8
DFN8
MN SUFFIX
CASE 506AA
5
1
4
3
1
4
(Note: Microdot may be in either location)
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