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參數(shù)資料
| 型號： | MC34065P-L |
| 廠商： | MOTOROLA INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | HIGH PERFORMANCE DUAL CHANNEL CURRENT MODE CONTROLLERS |
| 中文描述： | 0.4 A DUAL SWITCHING CONTROLLER, 500 kHz SWITCHING FREQ-MAX, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大小： | 419K |
| 代理商： | MC34065P-L |
MC34065–H, L MC33065–H, L
8
MOTOROLA ANALOG IC DEVICE DATA
Figure 16. Timing Diagram
Sync Input
Capacitor CT
Latch 1
“Set” Input
Compensation 1
Current Sense 1
Latch 1
“Reset” Input
Drive Output 1
Drive Output
2
Enable
Latch 2
“Set” Input
Compensation 2
Current Sense 2
Drive Output 2
Latch 2
“Reset” Input
The outputs do not contain internal current limiting,
therefore an external series resistor may be required to
prevent the peak output current from exceeding the
±
400 mA
maximum rating. The sink saturation (VOL) is less than 0.75 V
at 50 mA.
A separate Drive Ground pin is provided and, with proper
implementation, will significantly reduce the level of switching
transient noise imposed on the control circuitry. This
becomes particularly useful when reducing the Ipk(max) clamp
level. Figure 23 shows the proper ground connections
required for current sensing power MOSFET applications.
Drive Output 2 Enable Pin
This input is used to enable Drive Output 2. Drive Output 1
can be used to control circuitry that must run continuously
such as volatile memory and the system clock, or a remote
controlled receiver, while Drive Output 2 controls the high
power circuitry that is occasionally turned off.
Reference
The 5.0 V bandgap reference is trimmed to
±
2.0%
tolerance at TJ = 25
°
C. The reference has short circuit
protection and is capable of providing in excess of 30 mA for
powering any additional control system circuitry.
Design Considerations
Do not attempt to construct the converter on
wire–wrap or plug–in prototype boards.
High frequency
circuit layout techniques are imperative to prevent
pulse–width jitter. This is usually caused by excessive noise
pick–up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low current signal and high
current switch and output grounds returning on separate
paths back to the input filter capacitor. Ceramic bypass
capacitors (0.1
μ
F) connected directly to VCC and Vref may be
required depending upon circuit layout. This provides a low
impedance path for filtering the high frequency noise. All high
current loops should be kept as short as possible using
heavy copper runs to minimize radiated EMI. The Error Amp
compensation circuitry and the converter output
voltage–divider should be located close to the IC and as far
as possible from the power switch and other noise generating
components.
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