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參數資料
| 型號： | MC34129P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 穩壓器 |
| 英文描述： | HIGH PERFORMANCE CURRENT MODE CONTROLLERS |
| 中文描述： | 1 A SWITCHING CONTROLLER, 300 kHz SWITCHING FREQ-MAX, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁數： | 8/16頁 |
| 文件大小： | 347K |
| 代理商： | MC34129P |
MC34129 MC33129
OPERATING DESCRIPTION
8
MOTOROLA ANALOG IC DEVICE DATA
The MC34129 series are high performance current mode
switching regulator controllers specifically designed for use in
low power telecommunication applications. Implementation
will allow remote digital telephones and terminals to shed
their power cords and derive operating power directly from
the twisted pair used for data transmission. Although these
devices are primarily intended for use in digital telephone
systems, they can be used cost effectively in a wide range of
converter applications. A representative block diagram is
shown in Figure 18.
Oscillator
The oscillator frequency is programmed by the values
selected for the timing components RT and CT. Capacitor CT
is charged from the 2.5 V reference through resistor RT to
approximately 1.25 V and discharged by an internal current
sink to ground. During the discharge of CT, the oscillator
generates an internal blanking pulse that holds the lower
input of the NOR gate high. This causes the Drive Output to
be in a low state, thus producing a controlled amount of
output deadtime. Figure 1 shows Oscillator Frequency
versus RT and Figure 2 Output Deadtime versus Frequency,
both for given values of CT. Note that many values of RT and
CT will give the same oscillator frequency but only one
combination will yield a specific output deadtime at a give
frequency. In many noise sensitive applications it may be
desirable to frequency–lock one or more switching regulators
to an external system clock. This can be accomplished by
applying the clock signal to the Synch/Inhibit Input. For
reliable locking, the free–running oscillator frequency should
be about 10% less than the clock frequency. Referring to the
timing diagram shown Figure 19, the rising edge of the clock
signal applied to the Sync/Inhibit Input, terminates charging
of CT and Drive Output conduction. By tailoring the clock
waveform, accurate duty cycle clamping of the Drive Output
can be achieved. A circuit method is shown in Figure 20. The
Sync/Inhibit Input may also be used as a means for system
shutdown by applying a dc voltage that is within the range of
2.0 V to VCC.
PWM Comparator and Latch
The MC34129 operates as a current mode controller
whereby output switch conduction is initiated by the oscillator
and terminated when the peak inductor current reaches a
threshold level established by the output of the Error Amp or
Soft–Start Buffer (Pin 11). Thus the error signal controls the
peak inductor current on a cycle–by–cycle basis. The PWM
Comparator–Latch configuration used, ensures that only a
single pulse appears at the Drive Output during any given
oscillator cycle. The inductor current is converted to a voltage
by inserting the ground–referenced resistor RS in series with
the source of output switch Q1. The Ramp Input adds an
offset of 275 mV to this voltage to guarantee that no pulses
appear at the Drive Output when Pin 11 is at its lowest state.
This occurs at the beginning of the soft–start interval or when
the power supply is operating and the load is removed. The
peak inductor current under normal operating conditions is
controlled by the voltage at Pin 11 where:
V(Pin 11) – 0.275 V
Ipk =
RS
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the voltage at Pin 11 will be
internally clamped to 1.95 V by the output of the Soft–Start
Buffer. Therefore the maximum peak switch current is:
Ipk(max) =1.95 V – 0.275
RS
RS
1.675 V
=
When designing a high power switching regulator it
becomes desirable to reduce the internal clamp voltage in
order to keep the power dissipation of RS to a reasonable
level. A simple method which adjusts this voltage in discrete
increments is shown in Figure 22. This method is possible
because the Ramp Input bias current is always negative
(typically –120
μ
A). A positive temperature coefficient equal
to that of the diode string will be exhibited by Ipk(max). An
adjustable method that is more precise and temperature
stable is shown in Figure 23. Erratic operation due to noise
pickup can result if there is an excessive reduction of the
clamp voltage. In this situation, high frequency circuit layout
techniques are imperative.
A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Ramp Input with a time
constant that approximates the spike duration will usually
eliminate the instability; refer to Figure 25.
Error Amp and Soft–Start Buffer
A fully–compensated Error Amplifier with access to both
inputs and output is provided for maximum design flexibility.
The Error Amplifier output is common with that of the
Soft–Start Buffer. These outputs are open–collector (sink
only) and are ORed together at the inverting input of the PWM
Comparator. With this configuration, the amplifier that
demands lower peak inductor current dominates control of
the loop. Soft–Start is mandatory for stable startup when
power is provided through a high source impedance such as
the long twisted pair used in telecommunications. It
effectively removes the load from the output of the switching
power supply upon initial startup. The Soft–Start Buffer is
configured as a unity gain follower with the noninverting input
connected to Pin 12. An internal 1.0
μ
A current source
charges the soft–start capacitor (CSoft–Start) to an internally
clamped level of 1.95 V. The rate of change of peak inductor
current, during startup, is programmed by the capacitor value
selected. Either the Fault Timer or the Undervoltage Lockout
can discharge the soft–start capacitor.
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