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參數(shù)資料
| 型號(hào)： | MC3S12C32 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16-Bit Microcontroller |
| 中文描述： | 16位微控制器 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 520K |
| 代理商： | MC3S12C32 |
MOTOROLA
4
MC9S12C-Family
Figure 1 Block Diagram
32K, 64K, 96K, 128K Byte Flash/ROM
2K, 4K Byte RAM
MSCAN
VDDR
VDDX
VSSX
VDDA
VSSA
VRH
VRL
VRH
VRL
ATD
AN2
AN3
AN4
AN5
AN6
AN7
AN0
AN1
PAD3
PAD4
PAD5
PAD6
PAD7
PAD0
PAD1
PAD2
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
IOC0
IOC1
PT3
PT4
PT5
PT6
PT7
PT0
PT1
PT2
RXCAN
TXCAN
MISO
SCK
PS3
PS0
PS1
PS2
SS
SPI
P
P
D
P
D
Voltage Regulator
VDD1
VSS1
PWM
Module
Signals shown in
Bold
are not available on the 52 or 48 Pin Package
Signals shown in
Bold Italic
are available in the 52, but not the 48 Pin Package
D
VDDA
VSSA
Timer
Module
VSSR
RESET
EXTAL
XTAL
BKGD
R/W
LSTRB/TAGLO
ECLK
MODA/IPIPE0
MODB/IPIPE1
NOACC/XCLKS
XIRQ
IRQ
System
Integration
Module
(SIM)
HCS12
CPU
Periodic Interrupt
COP Watchdog
Clock Monitor
Single-wire Background
Debug12 Module
PLL
VSSPLL
XFC
VDDPLL
Multiplexed Address/Data Bus
Multiplexed
Wide Bus
P
P
P
P
P
P
P
P
TEST/VPP
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
P
P
P
P
P
P
P
P
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
PE3
PE4
PE5
PE6
PE7
PE0
PE1
PE2
DDRA
DDRB
PTA
PTB
D
P
Clock and
Reset
Generation
Module
VDD2
VSS2
PM3
PM4
PM5
PM0
PM1
PM2
P
D
PW2
PW3
PW4
PW5
PW0
PW1
PP3
PP4
PP5
PP6
PP7
PP0
PP1
PP2
P
D
PJ6
PJ7
P
D
VDD1,2
VSS1,2
VDDX
VSSX
Internal Logic 2.5V
VDDPLL
VSSPLL
PLL 2.5V
I/O Driver 5V
VDDA
VSSA
A/D Converter 5V
VDDR
VSSR
Voltage Regulator 5V & I/O
VRL is bonded internally to VSSA
for 52 and 48 Pin packages
MOSI
K
K
SCI
RXD
TXD
MUX
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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