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參數資料
| 型號： | MC44251FU |
| 廠商： | MOTOROLA INC |
| 元件分類： | ADC |
| 英文描述： | Triple 8-Bit Video ADC Three-State Outputs |
| 中文描述： | TRIPLE 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數： | 6/18頁 |
| 文件大小： | 273K |
| 代理商： | MC44251FU |
MC44251
6
MOTOROLA
td
CLK
IN
OUT
Figure 2. Conversion Timing Functional Characteristics
CIRCUIT OPERATION
GENERAL
The MC44251 contains three independent parallel ana-
log–to–digital converters (ADC). Each ADC consists of 256
latching comparators and an encoder. The MC44251 may be
used to convert RGB or YUV video information from an ana-
log to a digital format, or as a triple ADC for non–video in-
formation. For video processing performance enhancement,
each ADC has a dither generator with subsequent digital
correction designed into it. The dithering generator reduces
display degradation from granulation of the luminance
information caused by quantization errors of the digitizing
process. Each ADC is driven from a common clock and
receives common sync information from the HZ and VTN
pins. In addition, the VTN pin controls the dithering function
and disables the dithering generator when VTN is pulled low.
The sampling of the analog input signals occurs at the falling
edge of the clock signal, whereas the digital outputs change
state at the rising clock edge. The bias current of the
comparators is set by an external resistor. Input clamps allow
for ac coupling of the input signals.
CLAMP NETWORK
The MC44251 can be operated either dc coupled or ac
coupled. When dc coupled, the MC44251 will track the aver-
age dc level of the input waveform. For ac coupling, an
on–chip dc restoration circuit samples and adjusts the aver-
age dc level of the input signal. The MC44251 has three
selectable clamping levels for ac coupling.
The clamp levels
are selected by the MODE pin according to Table 1. In the
RGB mode, the clamping levels are set to 16/256, corre-
sponding to 6.3% of full range. In the YUV mode, the UV
clamping levels are set to 128/256 (50%) and the Y input to
either 16/256 or 64/256 (25%).
When input HZ (horizontal) is high, as illustrated in Fig-
ure 3a, the voltage difference between the analog input volt-
age and the clamp reference voltage is integrated within
each clamp network. At the falling edge of HZ, a latching
comparator senses the sign of the integrator output voltage.
Depending on this result, either a sinking or a sourcing cur-
rent is applied to the analog input pin as long as input HZ re-
mains low.
For video applications, the timing of HZ is critical to the
proper operation of the ADC. The frequency of HZ should be
locked to the line frequency of the video input. The pulse
width and timing of HZ with respect to the video signal is
shown in Figure 4. The top curve represents the horizontal
synchronizing and blanking interval for a video signal. The
pulse width of HZ (t
H
) should be less than the width of the
back porch (tBP) and coincident with it. In all cases, HZ must
return low before the end of the back porch (tBP).
Table 1. Clamping Levels
MODE
(Pin 35)
Application
Clamp Levels
Gin
16/256
Rin
16/256
Bin
16/256
L
RGB
H
YUV Mode Without Sync
Format
16/256
128/256
128/256
Open
YUV Mode With Sync
64/256
128/256
128/256
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