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參數資料
| 型號： | MC54-74HC175 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | Quad D Flip-Flop with Common Clock and Reset |
| 中文描述： | 四D觸發器與普通時鐘和復位拖鞋 |
| 文件頁數： | 2/7頁 |
| 文件大小： | 200K |
| 代理商： | MC54-74HC175 |
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
2
500
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC Package
– 65 to + 150
C
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
(Figure 1)
0
500
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
VCC = 4.5 V
VCC
Guaranteed Limit
– 55 to
3.15
Voltage
|Iout|
20
μ
A
4.5
3.15
3.15
6.0
1.2
1.2
1.2
VOH
Minimum High–Level Output
Vin = VIH or VIL
2.0
6.0
1.9
5.9
1.9
5.9
1.9
5.9
4.0 mA
5.2 mA
3.98
5.48
3.84
5.34
3.70
5.20
V
|Iout|
4.5
6.0
6.0
0.1
0.1
0.1
Vin = VIH or VIL
4.0 mA
4.5
0.26
0.33
0.40
|Iout|
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout)
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
VCC.
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