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參數資料
| 型號： | MC54-74HC374A |
| 廠商： | Motorola, Inc. |
| 英文描述： | Octal 3-State Non-Inverting D Flip-Flop |
| 中文描述： | 八路三態非反相D觸發器 |
| 文件頁數： | 2/8頁 |
| 文件大小： | 253K |
| 代理商： | MC54-74HC374A |
MC54/74HC374A
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
3–2
Functional operation should be restricted to the Recommended Operating Conditions.
Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
SSOP or TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Power Dissipation in Still Air, Plastic or Ceramic DIP
Tstg
Storage Temperature
TL
Lead Temperature, 1 mm from Case for 10 Seconds
V
SOIC Package
SSOP or TSSOP Package
300
450
mW
– 65 to + 150
C
(Ceramic DIP)
C
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
1000
500
400
ns
Symbol
b l
Parameter
Test Conditions
di i
V
25 C
U i
3.0
6.0
4.20
2.10
0.50
0.90
1.80
125 C
4.20
1.80
5.90
Voltage
6.0
6.0
|Iout|
20
μ
A
5.90
4.20
2.10
2.10
Maximum Low–Level Input
Voltage
|Iout|
20
μ
A
2.0
3.0
2.98
1.80
0.50
0.90
0.50
0.90
V
Minimum High–Level Output
Voltage
|Iout|
20
μ
A
2.0
1.90
5.90
3.70
1.90
1.90
V
|Iout|
4.5
3.84
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
(Vin or Vout)
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
VCC.
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