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參數資料
| 型號： | MC54HC00 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Quad 2-Input NAND Gate |
| 中文描述： | 四2輸入與非門 |
| 文件頁數： | 6/7頁 |
| 文件大小： | 167K |
| 代理商： | MC54HC00 |
MC54/74HC00A
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
6
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
MIN
8.55
3.80
1.35
0.35
0.40
1.27 BSC
MIN
0.337
0.150
0.054
0.014
0.016
0.050 BSC
MAX
8.75
4.00
1.75
0.49
1.25
MAX
0.344
0.157
0.068
0.019
0.049
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
0.19
0.10
0
°
5.80
0.25
0.25
0.25
7
°
6.20
0.50
0.008
0.004
0
°
0.228
0.010
0.009
0.009
7
°
0.244
0.019
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
–B–
P
7 PL
G
C
K
SEATING
D
14 PL
M
J
R
X 45
°
1
7
8
14
0.25 (0.010)
T
B
A
M
S
S
B
0.25 (0.010)
M
M
F
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MIN
4.90
4.30
–––
0.05
0.50
0.65 BSC
0.50
0.09
0.09
0.19
0.19
6.40 BSC
0
MAX
5.10
4.50
1.20
0.15
0.75
MIN
0.193
0.169
–––
0.002
0.020
0.026 BSC
0.020
0.004
0.004
0.007
0.007
0.252 BSC
0
MAX
0.200
0.177
0.047
0.006
0.030
INCHES
MILLIMETERS
0.60
0.20
0.16
0.30
0.25
0.024
0.008
0.006
0.012
0.010
8
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
S
U
0.15 (0.006) T
2X
L/2
S
U
M
0.10 (0.004)
V
S
T
L
–U–
SEATING
PLANE
0.10 (0.004)
–T–
ééé
ééé
ééé
SECTION N–N
DETAIL E
J J1
ééé
DETAIL E
F
M
–W–
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U
0.15 (0.006) T
–V–
14X REF
N
N
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MC54HC00AJ | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Quad 2-Input NAND Gate(High-Performance Silicon-Gate CMOS |
| MC54HC02A | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:QUAD 2-INPUT NOR GATE HIGH-PERFORMANCE SILICON-GATE CMOS |
| MC54HC02AJ | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:QUAD 2-INPUT NOR GATE HIGH-PERFORMANCE SILICON-GATE CMOS |
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| MC54HC04AJ | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Hex Inverter |
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