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參數資料
| 型號： | MC54HC00AJ |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quad 2-Input NAND Gate |
| 中文描述： | HC/UH SERIES, QUAD 2-INPUT NAND GATE, CDIP14 |
| 封裝： | CERAMIC, DIP-14 |
| 文件頁數： | 3/7頁 |
| 文件大小： | 167K |
| 代理商： | MC54HC00AJ |
MC54/74HC00A
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
DC CHARACTERISTICS
(Voltages Referenced to GND)
V
Guaranteed Limit
Symbol
Parameter
Condition
VCC
–55 to 25
°
C
≤
85
°
C
≤
125
°
C
Unit
VIH
Minimum High–Level Input Voltage
Vout = 0.1V or VCC –0.1V
|Iout|
≤
20
μ
A
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL
Maximum Low–Level Input Voltage
Vout = 0.1V or VCC – 0.1V
|Iout|
≤
20
μ
A
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
VOH
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
≤
20
μ
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin =VIH or VIL
|Iout|
≤
2.4mA
|Iout|
≤
4.0mA
|Iout|
≤
5.2mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOL
Maximum Low–Level Output
Voltage
Vin = VIH or VIL
|Iout|
≤
20
μ
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL
|Iout|
≤
2.4mA
|Iout|
≤
4.0mA
|Iout|
≤
5.2mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Iin
ICC
Maximum Input Leakage Current
Vin = VCC or GND
Vin = VCC or GND
Iout = 0
μ
A
6.0
±
0.1
±
1.0
±
1.0
μ
A
Maximum Quiescent Supply
Current (per Package)
6.0
1.0
10
40
μ
A
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6 ns)
V
Guaranteed Limit
Symbol
Parameter
VCC
–55 to 25
°
C
≤
85
°
C
≤
125
°
C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
Cin
Maximum Input Capacitance
10
10
10
pF
NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Buffer)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V, VEE = 0 V
22
pF
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