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參數資料
| 型號： | MC54HC164J |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-Bit Serial-Input/Parallel-Output Shift Register |
| 中文描述： | HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP14 |
| 封裝： | CERAMIC, DIP-14 |
| 文件頁數： | 3/7頁 |
| 文件大小： | 204K |
| 代理商： | MC54HC164J |
MC54/74HC164
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3
MOTOROLA
(Figures 1 and 4)
4.5
30
20
6.0
30
24
45
tPHL
Maximum Propagation Delay, Reset to Q
2.0
205
255
37
310
ns
tTHL
(Figures 1 and 4)
4.5
15
22
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
19
CPD
Power Dissipation Capacitance (Per Package)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
140
pF
Symbol
Parameter
V
25 C
125 C
tsu
Minimum Setup Time, A1 or A2 to Clock
2.0
50
85 C
75
Unit
ns
(Figure 3)
4.5
5
65
(Figure 2)
4.5
6.0
5
5
5
5
tw
Minimum Pulse Width, Clock
2.0
6.0
80
14
100
5
5
120
20
5
5
ns
Minimum Pulse Width, Reset
(Figure 2)
2.0
4.5
80
16
100
17
120
24
ns
(Figure 1)
4.5
6.0
500
400
500
400
20
500
400
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