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參數資料
| 型號： | MC54HC4016A |
| 廠商： | Motorola, Inc. |
| 英文描述： | Quad Analog Switch/Multiplexer/Demultiplexer |
| 中文描述： | 四模擬開關/復用器/解復用器 |
| 文件頁數： | 4/12頁 |
| 文件大小： | 334K |
| 代理商： | MC54HC4016A |
MC54/74HC4016A
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
3–4
Analog I/O
35
35
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
—
35
CPD
Power Dissipation Capacitance (Per Switch)* (Figure 13)
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
15
pF
(Figure 5)
Increase fin Frequency Until dB Meter Reads – 3 dB
VCC
12.0
25 C
160
(Figure 6)
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600
, CL = 50 pF
fin = 1.0 MHz, RL = 50
, CL = 10 pF
9.0
12.0
– 50
– 50
4.5
12.0
– 40
– 40
—
Feedthrough Noise, Control to Switch
(Figure 7)
Adjust RL at Setup so that IS = 0 A
4.5
9.0
60
130
9.0
65
—
Crosstalk Between Any Two Switches
fin
Sine Wave
4.5
12.0
– 70
– 70
dB
4.5
– 80
(Figure 14)
THD = THDMeasured – THDSource
* Guaranteed limits not tested. Determined by design and verified by qualification.
VIS = 11.0 VPP sine wave
12.0
0.04
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