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參數資料
| 型號： | MC54HC74AJ |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual D Flip-Flop with Set and Reset |
| 中文描述： | HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14 |
| 封裝： | CERAMIC, DIP-14 |
| 文件頁數： | 2/7頁 |
| 文件大小： | 229K |
| 代理商： | MC54HC74AJ |
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
3–2
500
450
SOIC Package
TSSOP Package
Lead Temperature, 1 mm from Case for 10 Seconds
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
(Ceramic DIP)
300
0
400
VCC = 6.0 V
Symbol
Parameter
Test Conditions
V
25 C
85 C
125 C
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20
μ
A
2.0
4.5
1.5
3.15
1.5
3.15
1.5
3.15
Unit
Voltage
20
μ
A
4.5
6.0
1.35
1.8
1.35
1.8
1.35
1.8
V
Minimum High–Level Output
Vin = VIH or VIL
2.0
1.9
1.9
1.9
5.2 mA
5.48
5.34
5.2
VOL
Maximum Low–Level Output
Vin = VIH or VIL
|Iout|
6.0
2.0
0.1
0.1
0.1
5.2 mA
0.26
0.33
0.4
V
6.0
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout)
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
VCC.
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