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參數資料
| 型號： | MC54HCT08 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Quad 2-Input AND Gate with LSTTL-Compatible Inputs |
| 中文描述： | 四2輸入與門的輸入通道兼容輸入 |
| 文件頁數： | 2/5頁 |
| 文件大小： | 170K |
| 代理商： | MC54HCT08 |
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
2
DC Output Current, per Pin
PD
Power Dissipation in Still Air,Plastic or Ceramic DIP
25
±
50
mA
750
mA
mW
Functional operation should be restricted to the Recommended Operating Conditions.
Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
(Ceramic DIP)
300
Symbol
VCC
Vin, Vout
TA
tr, tf
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Min
4.5
0
Max
5.5
VCC
+ 125
Unit
V
V
Operating Temperature, All Package Types
– 55
C
Input Rise and Fall Time (Figure 1)
0
500
ns
– 55 to
VCC
Voltage
20
μ
A
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20
μ
A
|Iout|
4.0 mA
Vin = VIH or VIL
5.5
2.00
2.00
2.00
Maximum Low–Level Input
Voltage
4.5
5.5
0.80
0.80
0.80
0.80
0.80
0.80
V
4.5
3.98
3.84
3.70
VOL
Maximum Low–Level
4.5
0.10
0.10
0.10
V
Current
ICC
Maximum Quiescent Supply
Vin = VCC or GND
Vin = VCC or GND,
5.5
1
10
40
Supply Current
μ
A
≥
–55 C
25 to 125 C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout)
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
VCC.
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