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參數資料
| 型號： | MC68160CFB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 網絡接口 |
| 英文描述： | 3.0V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP52 |
| 封裝： | PLASTIC, TQFP-52 |
| 文件頁數： | 21/30頁 |
| 文件大小： | 372K |
| 代理商： | MC68160CFB |
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MC68160 MC68160B MC68160C
21
MOTOROLA ANALOG IC DEVICE DATA
TPTX+/–
CLSN
1.5V
2V
1.5V
TPSQEL
1.5V
Figure 29. TPTX SQE (CLSN) Timing (End of Frame)
t173
t171
t170
t172
TP RECEIVE SWITCHING
Characteristic
Symbol
Min
Max
Unit
Differential Input Voltage Range Unconditional Squelch (Note 1)
(1.8 V < Input Common Mode Voltage < 3.2 V)
VIDFSTP
0
|264|
mV
Positive or Negative Differential Input Pulse Width for Conditional Receive Unsquelch
(See Figure 31)
t180
20
30
ns
TPRX to RCLK Bit Loss at start of packet (See Figure 32)
t181
t182
t183
t186
t187
–
10
Bits
TPRX to RCLK Steady State Propagation Delay (See Figure 32)
–
400
ns
TPRX to RX Start Up Delay (See Figure 32)
–
1.5
μ
s
TPRX held high from last valid positive transition (See Figure 33)
230
–
ns
RENA Deassertion Delay from last valid positive transition of TPRX Pair
(MC68160, MC68160C) (See Figure 33)
–
350
ns
RENA Deassertion Delay from last valid positive transition of TPRX Pair (MC68160B)
t187
–
400
ns
TP RECEIVE LINK INTEGRITY SWITCHING
Required Pulse Width Range to be recognized as a Link Pulse (Note 2)
t200
t201
50
200
ns
Last TPRX activity to high state TPLIL Output
(Receive Link Loss Timeout Interval)
100
150
ms
Receive Link Beat Separation
Minimum Range (Note 3)
Maximum Range (Note 4)
t202
t203
3.0
100
7.0
150
ms
NOTES:
1. Measured with Test Load H attached to the receive pins.
2. Measured at the receive pins.
3. Link beats closer in time to this range of values are considered noise, and are rejected.
4. Link beats further apart in time than this range of values are not considered consecutive, and are rejected.
t180
t180
TPRX
–330mV
+330mV
0mV
200
μ
H
100
1.0
μ
H
1.0
μ
H
100pF
100pF
Line
Figure 30. Test Load H
Figure 31. TPRX Input Switching
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