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參數資料
| 型號： | MC68181 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Roaming FLEXchip(漫游式FLEX芯片) |
| 中文描述： | 漫游FLEXchip（漫游式FleX創建芯片） |
| 文件頁數： | 2/4頁 |
| 文件大小： | 45K |
| 代理商： | MC68181 |
2
MC68181P/D, Preliminary
MOTOROLA
MC68181
Flex chip Features
PRELIMINARY
the receiver control sequences.
FLEX chip FEATURES
Roaming FLEX paging protocol signal processor
Sixteen programmable user address words
Sixteen fixed temporary addresses
Sixteen operator messaging addresses
1600, 3200, and 6400 bits per second (bps) decoding
Any-phase or single-phase decoding
Uses standard Serial Peripheral Interface (SPI) in Slave mode
Wide operating voltage range from 3.3 V down to 1.8 V
Allows low current Stop mode operation of host processor
Highly programmable receiver control
Real time clock time base
FLEX fragmentation, and group messaging support
Real time clock over-the-air update support
Compatible with synthesized receivers
SSID and NID Roaming support
Low battery indication (external detector)
32-pin Thin Quad Flat Pack (TQFP) package
Backward compatible with standard FLEX chip Signal Processor MC68175
Operating temperature range 0o to +70oC (32o to 158oF)
FLEX chip SYSTEM DESIGN
The Roaming FLEX chip IC connects to a receiver capable of converting a 4-level audio signal
into a 2-bit digital signal (see
Figure 2
). The FLEX chip IC has eight receiver control lines used for
tuning, warming up, and shutting down a receiver in stages. Dual bandwidth control signals for
two post-detection filter bandwidths are used for receiving the two FLEX symbol rates. The
FLEX chip interfaces to a back-end host MCU through a standard SPI, and provides a 38.4 kHz
clock output capable of driving other devices. It has a 1 minute timer that offers low power
support for time of day function on the host, and the ability to detect a low battery signal during
All data communicated between the FLEX chip IC and the host MCU is transmitted on the SPI in
32-bit packets. Each packet consists of an 8-bit ID followed by 24 bits of information. The FLEX
chip IC uses the SPI bus in Full Duplex mode, so whenever a packet communication occurs, the
data in both directions is valid packet data.
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