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參數資料
| 型號： | MC68328 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | DragonBall 32-Bit Microprocessor( DragonBall32位微處理器) |
| 中文描述： | 32-BIT, 16.67 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數： | 3/8頁 |
| 文件大小： | 27K |
| 代理商： | MC68328 |
DragonBall Power Modes
Motorola
3
frequency select register. Note that the VCO frequency can be maintained at its default value
while achieving power saving requirements for the system.
Sysclk—This clock signal is derived from the VCO through a divider. By default the
MC68328 divides by 1, generating a Sysclk frequency of 16.58MHz after reset. By default the
MC68EZ328 divides by 2 (EZ328 has a 1-bit Prescaler which is set by default), so Sysclk is
Normal Mode
8.29MHz after reset. The Sysclk output is applied to all DragonBall peripheral modules except
the RTC, which is clocked directly from the external 32KHz crystal.
Pixel clock—This clock is used for the LCD pixel generation. It is separated from Sysclk so
that changing the system-clock frequency for power saving will not affect the LCD screen
refresh rate.
CPU clock—This clock signal is input to the CPU core. Since the CPU consumes a major
portion of overall power, changing the CPU clock frequency and burst duty cycle will directly
affect the DragonBall power consumption.
In normal mode the system is running at its highest frequency, and the DragonBall consumes
maximum power. The maximum system clock frequency for both the MC68328 and MC68EZ328 is
16.58Mhz. The 68K core performance at this frequency is 2.7 million instructions per second (MIPS).
If the system requires a peak performance lower than 2.7 MIPS, a lower system clock frequency can
be used by programming the system-clock divider accordingly.
The system-clock frequency can be rescaled from 16MHz down to 1MHz for the MC68328 by
programming the system-clock divider bits in the PLL control register ($FFF200). For the
MC68EZ328, the system-clock frequency can be scaled down to 512KHz by programming the
prescaler and divider bits.
Because most of the modules, such as the UART, SPI, TIMER, and PWM, use the system clock for bit
rate generation, changing the system-clock frequency will also change the system timing. Therefore,
once a system-clock frequency is selected, it should not be changed during system operation. Burst
and DOZE modes are then used for power saving.
Burst Mode
If the user wants to keep the modules enabled at a high system-clock frequency during normal
operation without requiring maximum CPU performance, burst CPU clock-control mode can be
enabled. The period of a burst is 1 ms, and the duty-cycle of a burst is controlled by the value of the
WIDTH bits in the power control register. The user can choose from 1/31 to 31/31 of 1 ms of CPU
active time for every 1 ms burst period. A WIDTH value of zero will place the CPU in DOZE mode.
Smaller values of WIDTH will reduce system power consumption.
Burst mode is often used in data-polling applications. Burst mode is entered by setting the PC EN bit
and program the WIDTH bits of the power control register. Burst mode is disabled automatically when
there is an interrupt event. Clearing the PC EN bit will also disable burst control.
DOZE Mode
For many PDA applications, the system takes only a little time to process tasks the user requests, after
which the system waits again for user commands, such as a touch screen input. During the waiting
period, some peripherals like the LCD screen must be active. Therefore, the developer can stop the
CPU in these waiting periods using DOZE mode.
As mentioned before, DOZE mode is entered by setting the PC EN bit and clearing the WIDTH bits of
the power control register. DOZE mode is disabled automatically when there is an interrupt event.
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相關代理商/技術參數 |
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| MC68328P | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Integrated Portable System Processor-DragonBall |
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