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參數資料
| 型號： | MC68360CRC25 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | QUad Integrated Communications Controller Users Manual |
| 中文描述： | 32-BIT, 25 MHz, RISC MICROCONTROLLER, CPGA241 |
| 封裝： | PGA-241 |
| 文件頁數： | 11/28頁 |
| 文件大小： | 159K |
| 代理商： | MC68360CRC25 |
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MOTOROLA
MC68360 USER’S MANUAL ERRATA
11
11. Error in Signal Name.
On Page 7-73, section 7.8.4.5, the four strobe signal names L1STA1, L1STA2, L2STB1, and
L1STB2 in the SSEL1-SSEL4 should be replaced with L1ST1, L1ST2, L1ST3, and L1ST4.
12. Typo in SI Mode Register.
On page 7-81, section7.8.5.2, the bit definition of Grant Mode for TDM A or B has a typo and
should be replaced with the following text:
“1 = IDL mode. A GRANT mechanism is supported if the corresponding GR1-GR4 bits
in the SICR register are set. The grant is a sample of the L1GRx pin while
L1TSYNCx is asserted. This GRANT mechanism implies the IDL access controls
for transmission on the D channel. Refer to 7.8.6.2 IDL Interface Programming.”
13. Typo on Time Slot Assigner Examples.
On pages 7-83 to 7-85, the acronym for frame sync delay was printed incorrectly. The
correct acronym is FSD, not SFD.
14. Typo in SI Status Register.
On page 7-87, section 7.8.5.5, first paragraph, second sentence, “The value of this register
is valid only when the corresponding bit in the SIGMR is clear.” The acronym SIGMR should
have been SICMR.
15. Errata and missing note in GSMR
On page 7-113, the note under the description of CDP was not clear and should be replaced
with the following.
NOTE
This bit must be set if this SCC is used in transparent mode and
must be cleared when used and non-transparent mode.
The same note should be added below the description of CTSP.
16. Clarification of TDCR—Transmit Divide Clock Rate Description.
One page 7-117, section 7.10.2, replace the second sentence of the TDCR description
beginning “If the DPLL is not used …” with the following:
“To bypass the DPLL, choose the 1x value, except in asynchronous UART mode where
8x,16x, or 32x still must be used.”
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關PDF資料 |
PDF描述 |
|---|---|
| MC68360FE25 | QUad Integrated Communications Controller Users Manual |
| MC68360FE25V | QUad Integrated Communications Controller Users Manual |
| MC68360FE33 | QUad Integrated Communications Controller Users Manual |
| MC68360RC25 | QUad Integrated Communications Controller Users Manual |
| MC68360RC25V | QUad Integrated Communications Controller Users Manual |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MC68360CRC25L | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68360CVR25L | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68360CVR25LR2 | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68360CZP25L | 功能描述:IC MPU QUICC 25MHZ 357-PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M683xx 標準包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點:- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，FCBGA 供應商設備封裝:783-FCPBGA（29x29） 包裝:托盤 |
| MC68360CZP25LR2 | 功能描述:IC MPU QUICC 25MHZ 357-PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M683xx 標準包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點:- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，FCBGA 供應商設備封裝:783-FCPBGA（29x29） 包裝:托盤 |
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