
MOTOROLA
90
MC68CK338
MC68CK338TS/D
The FCSM counter register is a read/write register. A read returns the current value of the counter. A
write loads the counter with the specified value. The counter then begins incrementing from this new
value.
6.8 Modulus Counter Submodule (MCSM)
The modulus counter submodule (MCSM) is an enhancement of the FCSM. The MCSM contains a 16-
bit modulus latch, a 16-bit loadable up-counter, counter loading logic, a clock selector, a time base bus
driver, and an interrupt interface. A modulus latch gives the additional flexibility of recycling the counter
at a count other than 64-Kbyte clock cycles. The state of the modulus latch is transferred to the counter
when an overflow occurs or when a user-specified edge transition occurs on an external input pin. In
addition, a write to the modulus counter simultaneously loads both the counter and the modulus latch
with the specified value. The counter then begins incrementing from this new value.
Three MCSMs are contained in the CTM6.
Figure 21
shows a block diagram of the MCSM.
NOTE
In order to count, the MCSM requires the CPSM clock signals to be present. On
coming out of reset, the MCSM does not count internal or external events until the
prescaler in the CPSM starts running (when the software sets the PRUN bit). This
allows all counters in the CTM6 submodules to be synchronized.
Figure 21 MCSM Block Diagram
FCSM3CNT —
FCSM Counter Register
$YFF41A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
INTERRUPT
CONTROL
CLOCK
INPUT PIN
CTMC
CTM MCSM BLOCK
16-BIT UP COUNTER
IL2
IL1
IL0
IARB3
COF
EDGE
DETECT
TIME BASE BUSES
CLOCK
SELECT
IN2
CLK1 CLK0
CLK2
OVERFLOW
BUS
SELECT
CONTROL REGISTER BIT
CONTROL REGISTER BITS
6 CLOCKS (PCLKX) FROM PRESCALER
SUBMODULE BUS
MODULUS
CONTROL
MODULUS REGISTER
CONTROL REGISTER BITS
EDGEN EDGEP
EDGE
DETECT
MODULUS LOAD
INPUT PIN CTML
IN1
CONTROL REGISTER BITS
WRITE
BOTH
DRVA DRVB
CONTROL REGISTER BITS
TBBA
TBBB
MODULUS
LOAD INPUT
PIN CTML
CONTROL REGISTER BIT