
7-16
M68040 USER’S MANUAL
MOTOROLA
(Except MC68EC040 and MC68EC040V)
for information on the M68040 and
MC68LC040 memory units and
Appendix B MC68EC040
for information on the
MC68EC040 memory unit.
The processor asserts
TS
during C1 to indicate the beginning of a bus cycle. If not
already asserted from a previous bus cycle,
TIP
is also asserted at this time to indicate
that a bus cycle is active.
Clock 2 (C2)
During the first half of the first clock after C1, the processor negates
TS
. The selected
device uses R/
W
, SIZ1, and SIZ0 to place the data on the data bus. (The first transfer
must supply the long word at the corresponding long-word boundary.) Concurrently, the
selected device asserts
TA
and either negates or asserts
TBI
to indicate it can or cannot
support a burst transfer. At the end of the first clock cycle after C1, the processor
samples the level of
TA
,
TBI
, and
TCI
and latches the current value on the data bus. If
TA
is asserted, the transfer terminates and the data is passed to the appropriate
memory unit. If
TA
is not recognized asserted, the processor ignores the data and
inserts wait states instead of terminating the transfer. The processor continues to
sample
TA
,
TBI
, and
TCI
on successive rising edges of BCLK until
TA
is recognized
asserted. The latched data and the level on
TCI
are then passed to the appropriate
memory unit.
If
TBI
was negated with
TA
, the processor continues the cycle with C3. Otherwise, if
TBI
was asserted, the line transfer is burst inhibited, and the processor reads the remaining
three long words using long-word read bus cycles. The processor increments A3 and
A2 for each read, and the new address is placed on the address bus for each bus cycle.
Refer to
7.4.1 Byte, Word, and Long-Word Read Transfers
for information on long-
word reads. If no wait states are generated, a burst-inhibited line read completes in
eight clocks instead of the five required for a burst read.
Clock 3 (C3)
The processor holds the address and transfer attribute signals constant during C3. The
selected device must increment A3 and A2 to reference the next long word to transfer,
place the data on the data bus, and assert
TA
. At the end of C3, the processor samples
the level of
TA
and latches the current value on the data bus. If
TA
is asserted, the
transfer terminates, and the second long word of data is passed to the appropriate
memory unit. If
TA
is not recognized asserted at the end of C3, the processor ignores
the latched data and inserts wait states instead of terminating the transfer. The
processor continues to sample
TA
on successive rising edges of BCLK until it is
recognized. The latched data is then passed to the appropriate memory unit.
Clock 4 (C4)
This clock is identical to C3 except that once
TA
is recognized asserted, the latched
value corresponds to the third long word of data for the burst.