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參數資料
| 型號： | MC68HC05K3 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數： | 8/56頁 |
| 文件大小： | 311K |
| 代理商： | MC68HC05K3 |
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Application Note
Software Implementation
AN1288
8
MOTOROLA
The PEEPROM status/control register (PESCR), illustrated in
Figure 2
,
contains the control and status bits used in reading and programming
the PEEPROM.
When programming the PEEPROM, K3EEPROG programs the entire
array with 16 bytes of data entered by the user. K3EEPROG stores this
data in locations $C0–$CF in the emulator’s memory.The algorithm for
programming one PEEPROM bit is outlined in the General Release
Specification for the MC68HC(8)05K3 (HC805K3GRS/D). Since
K3EEPROG deals with data in bytes, the programming algorithm must
be modified to program eight bits at a time. The PEEPROM facilitates
this by providing the PEPCZF bit, bit 0, in the PESCR status/control
register. This bit is set whenever a bit in the 0 column is being accessed.
If the column 0 bit is taken to be the least significant bit of a row or byte,
it is possible to differentiate between the end of one row and the start of
the following row.
The algorithm developed for programming the PEEPROM is:
1.
Load the row (byte) counter variable with a value of 16.
2.
Bulk erase the PEEPROM.
a.
Set the CPEN bit in the PECSR control/status register.
b.
Set the PEBULK bit in the PECSR control/status register.
c.
Delay 30 milliseconds.
d.
Clear the CPEN bit in the PECSR control/status register.
e.
Clear the PEBULK bit in the PECSR control/status register.
3.
Initialize the DATA_PTR variable.
4.
Load the accumulator with data contained in the location pointed
to by address $C0 plus the offset in the DATA_PTR variable.
Address: $0F
Bit 7
6
5
4
3
2
1
Bit 0
PEDATA PEBULK
PEPGM
PEBYTE
CPEN
CPCLK
0
PEPCZF
Figure 2. PESCR Status/Control Register
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