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參數資料
| 型號： | MC68HC05T7B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁數： | 1/109頁 |
| 文件大小： | 9008K |
| 代理商： | MC68HC05T7B |
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Technical Data
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 3.0
100
External Interrupt Module (IRQ)
MOTOROLA
External Interrupt Module (IRQ)
9.4 Operation
The interrupt request/programming voltage pin (IRQ/VPP) and port A
pins 0–3 (PA0–PA3) provide external interrupts. The PIRQ bit in the
mask option register (MOR) enables PA0–PA3 as IRQ interrupt sources,
which are combined into a single OR’ing function to be latched by the
IRQ latch. Figure 9-1 shows the structure of the IRQ module.
After completing its current instruction, the CPU tests the IRQ latch. If the
IRQ latch is set, the CPU
then tests the I bit in the condition code register and the IRQE bit in the
IRQ status and control register. If the I bit is clear and the IRQE bit is set,
the CPU then begins the interrupt sequence. This interrupt is serviced
by the interrupt service routine located at $07FA and $07FB.
The CPU clears the IRQ latch while it fetches the interrupt vector, so that
another external interrupt request can be latched during the interrupt
service routine. As soon as the I bit is cleared during the return from
interrupt, the CPU can recognize the new interrupt request. Figure 9-3
shows the sequence of events caused by an interrupt.
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