- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371051 > MC68HC11K4CFN2 (MOTOROLA INC) Technical Summary 8-Bit Microcontroller PDF資料下載
參數(shù)資料
| 型號： | MC68HC11K4CFN2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Technical Summary 8-Bit Microcontroller |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 47/80頁 |
| 文件大小： | 420K |
| 代理商： | MC68HC11K4CFN2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁當(dāng)前第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
47
NOTE
In expanded and special test modes, chip-select circuitry forces the I/O state to be
an output for each port H pin associated with an enabled chip select. In any mode,
PWM circuitry forces the I/O state to be an output for each port H line associated
with an enabled pulse width modulator channel. In these cases, data direction bits
are not changed and have no effect on these lines. DDRH reverts to controlling the
I/O state of a pin when the associated function is disabled. Refer to
4.3 Memory
Expansion and Chip Selects
and
12 Pulse-Width Modulation Timer
for further
information.
Port G pins reset to high-impedance inputs with selectable internal pull-up resistors. In expanded and
special test modes PG7 becomes R/W. Refer to PGAR register description.
DDG[7:0] —Data Direction for Port G
0 = Configure corresponding I/O pin for input only
1 = Configure corresponding I/O pin for output
In expanded and test modes, bit 7 is configured for R/W, forcing the state of this pin to be an output
although the DDRG value remains zero. Refer to PGAR register description.
Bits [7:6] —Not implemented
Always read zero
PGAR[5:0] —Port G Pin Assignment Bits [5:0]
0 = Corresponding port G pin is general-purpose I/O
1 = Corresponding port G pin is memory expansion address line (XA[18:13])
NOTE
Each PGAR bit forces the I/O state to be an output for each port G pin associated
with an enabled expansion address line. In this case, data direction bits are not
changed and have no effect on these lines. DDRG reverts to controlling the I/O
state of a pin when the associated function is disabled. Refer to
4.1 Memory Ex-
pansion
for further information.
PORTG
—Port G Data
$007E
Bit 7
6
5
4
3
2
1
Bit 0
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
RESET:
I
I
I
I
I
I
I
I
Alt. Pin
Func.:
R/W
—
XA18
XA17
XA16
XA15
XA14
XA13
DDRG
—Data Direction Register for Port G
$007F
Bit 7
6
5
4
3
2
1
Bit 0
DDG7
DDG6
DDG5
DDG4
DDG3
DDG2
DDG1
DDG0
RESET:
0
0
0
0
0
0
0
0
PGAR
—
Port G Assignment
$002D
Bit 7
6
5
4
3
2
1
Bit 0
$
0
02D
—
—
PGAR5
PGAR4
PGAR3
PGAR2
PGAR1
PGAR0
RESET:
0
0
0
0
0
0
0
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC11K4CFN3 | Technical Summary 8-Bit Microcontroller |
| MC68HC11K1VFU2 | 8-BIT MICROCONTROLLER |
| MC68HC11K4VFU2 | MNX Series Enclosure; NEMA Type:1, 2, 4, 4X, 6, 12, 13; Enclosure Material:Polycarbonate; External Height:5.1"; External Width:3"; External Depth:3.9" |
| MC68HC11K1VFU3 | MNX Series Enclosure; NEMA Type:1, 2, 4, 4X, 6, 12, 13; Enclosure Material:Polycarbonate; External Height:10"; External Width:7.1"; External Depth:2.5"; Enclosure Color:Light Gray; Approval Bodies:UL, CSA; Cover Color:Light Gray RoHS Compliant: Yes |
| MC68HC11K4VFU3 | Technical Summary 8-Bit Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC11K4CFN3 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Technical Summary 8-Bit Microcontroller |
| MC68HC11K4CFN4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC11K4CFS2 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC11K4CFS3 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC11K4CFS4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。