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參數資料
| 型號： | MC68HC11K4VFU4 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Technical Summary 8-Bit Microcontroller |
| 中文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數： | 31/80頁 |
| 文件大小： | 420K |
| 代理商： | MC68HC11K4VFU4 |
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M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
31
4.3.1 Program Chip Select (CSPROG)
The program chip select (CSPROG) is active in the range of memory where the main program exists.
CSPROG is enabled out of reset in all modes. After reset in normal mode, the PCS stretch select bit is
set to provide one cycle of stretch so that slow memory devices can be used.
4.3.2 I/O Chip Select (CSIO)
The I/O chip select (CSIO) is programmable for a four Kbyte size located at addresses $1000 to $1FFF
or eight Kbyte size located at addresses $0000 to $1FFF. Polarity of the active state is programmable
for active high or active low. Clock stretching can be set from zero to three cycles.
CSIO
Enable
Valid
Polarity
Size
Start Address
Stretch
IOEN in CSCTL —1 = On, off at reset (0)
IOCSA in CSCTL —1 = Address valid, 0 = E valid
IOPL in CSCTL —1 = Active high, 0 = Active low
IOSZ in CSCTL —1 = 4K ($1000–$1FFF), 0 = 8K ($0000–$1FFF)
Fixed (see Size)
IO1SA:IO1SB in CSCSTR —0, 1, 2, or 3 E clocks
CSPROG
Enable
Valid
Polarity
Size
PSCEN in CSCTL —1 = On, ON at reset
Fixed (Address valid)
Fixed (Active low)
PCSZA:PCSZB in CSCTL —
0:0 = 64K ($0000–$FFFF)
0:1 = 32K ($8000–$FFFF)
1:0 = 16K ($C000–$FFFF)
1:1 = 8K ($E000–$FFFF)
Start Address
Stretch
Priority
Fixed (see Size)
PCSA:PCSB in CSCSTR —0, 1, 2, or 3 E clocks
GCSPR in CSCTL —
1 = CSGPx above CSPROG
0 = CSPROG above CSGPx
CSGP1,
CSGP2
Enable
Valid
Polarity
Size
Set size to 0K to disable
GxPOL in GPCS1C (GPCS2C) —1 = Address valid, 0 = E valid
GxAV in GPCS1C (GPCS2C) —1 = Active high, 0 = Active low
Refer to GPCS1C (GPCS2C) —2K to 512K in nine steps, 0K = dis-
able, can also follow memory expansion window 1 or window 2
Refer to GPCS1A (GPCS2A)
Refer to CSCSTR —0, 1, 2, or 3 E clocks
G1DG2 in GPCS1C allows CSGP1 and CSGP2 to be connected to
an internal OR gate and driven out the CSGP2 pin.
Start Address
Stretch
Other
G1DPC in GPCS1C allows CSGP1 and CSPROG to be connected to
an internal OR gate and driven out the CSPROG pin.
G2DPC in GPCS2C allows CSGP2 and CSPROG to be connected to
an internal OR gate and driven out the CSPROG pin.
MXGS2 in MMSIZ allows CSGP2 to follow either 64K CPU addresses
or 512K expansion addresses.
MXGS1 in MMSIZ allows CSGP1 to follow either 64K CPU addresses
or 512K expansion addresses.
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