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參數資料
| 型號： | MC68HC901P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 外設及接口 |
| 英文描述： | Multi-Function Peripheral |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PDIP48 |
| 封裝： | PLASTIC, DIP-48 |
| 文件頁數： | 27/73頁 |
| 文件大小： | 274K |
| 代理商： | MC68HC901P |
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Interrupt Structure
4-4
MC68HC901 USER’S MANUAL
MOTOROLA
4.3 INTERRUPT CONTROL REGISTERS
MFP interrupt processing is managed by the enable registers A and B, interrupt pending
registers A and B, and interrupt mask registers A and B. These registers allow the
programmer to enable or disable individual interrupt channels, mask individual interrupt
channels, and access pending interrupt status information. In-service registers A and B
allow interrupts to be nested as described in
interrupt control registers are shown in the following paragraphs.
Section 4.4 Nesting MFP Interrupts
. The
4.3.1 Interrupt Enable Registers (IERA, IERB)
The interrupt channels are individually enabled or disabled by writing a one or a zero,
respectively, to the appropriate bit of interrupt enable register A or B (IERA or IERB). The
processor may read these registers at any time.
When a channel is enabled, interrupts received on the channel will be recognized by the
MFP, and IRQ will be asserted to the processor indicating that interrupt service is required.
On the other hand, a disabled channel is completely inactive; interrupts received on the
channel are ignored by the MFP.
Writing a zero to a bit of interrupt enable register A or B will cause the corresponding bit of
the interrupt pending register to be cleared. This will terminate all interrupt service requests
for the channel and also negate IRQ unless interrupts are pending from other sources.
Disabling a channel, however, does not affect the corresponding bit in interrupt in-service
registers A or B. So, if the MFP is in the software end-of-interrupt mode (refer to
4.4.3 Software End-Of-Interrupt Mode
) and an interrupt is in service when a channel is
disabled, the in-service bit of that channel will remain set until cleared by software.
Section
GPIP7-GPIP6 — General Purpose Interrupt Enable
1 = Enable.
0 = Disable.
Timer A — Timer A Interrupt Enable
1 = Enable.
0 = Disable.
Receiver Buffer Full — Receiver Buffer Full Interrupt Enable
1 = Enable.
0 = Disable.
IERA REGISTER
BIT
7
6
5
4
3
2
1
0
FIELD
GPIP7
GPIP6
TIMER A
RCV
BUFFER
FULL
RCV
ERROR
XMIT
BUFFER
EMPTY
XMIT
ERROR
TIMER B
RESET
0
0
0
0
0
0
0
0
ADDR
$07
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