
MOTOROLA
12-20
CONFIGURABLE TIMER MODULE 7
MC68HC16R1/916R1
USER’S MANUAL
NOTE
A duty cycle of 100% is not possible when the output period is set to
65536 PWM clock periods (which occurs when PWMB2 is set to
$0000). In this case, the maximum duty cycle is 99.998% (100 x
65535/65536).
Even when the duty cycle is 0% or 100%, the PWMSM counter con-
tinues to count.
12.10.11 PWMSM Registers
The PWMSM contains a status/interrupt/control register, a period register, a pulse
width register, and a counter register. All unused bits and reserved address locations
return zero when read. Writes to unused bits and reserved address locations have no
effect. The CTM7 contains two PWMSMs, each with its own set of registers. Refer to
D.7.16 PWM Status/Interrupt/Control Register
,
D.7.17 PWM Period Register
,
D.7.18 PWM Pulse Width Register
, and
D.7.19 PWM Counter Register
for informa-
tion concerning PWMSM register and bit descriptions.
12.11 CTM7 Interrupts
The CTM7 is able to generate as many as 11 requests for interrupt service. Each sub-
module capable of requesting an interrupt can do so on any of seven levels. Submod-
ules that can request interrupt service have a 3-bit level number and a 1-bit arbitration
number that is user-initialized.
The 3-bit level number selects which of seven interrupt signals on the IMB are driven
by that submodule to generate an interrupt request. Of the four priority bits provided
by the IMB to the CTM7 for interrupt arbitration, one of them comes from the chosen
submodule, and the BIUSM provides the other three. Thus, the CTM7 can respond
with two of the 15 possible arbitration numbers.
During the IMB arbitration process, the BIUSM manages the separate arbitration
among the CTM7 submodules to determine which submodule should respond. The
CTM7 has a fixed hardware prioritization scheme for all submodules. When two or
more submodules have an interrupt request pending at the level being arbitrated on
the IMB, the submodule with the lowest number (also the lowest status/interrupt/con-
trol register address) is given the highest priority to respond.
If the CTM7 wins arbitration, it responds with a vector number generated by concate-
nating VECT[7:6] in BIUMCR and the six low-order bits specified by the number of the
submodule requesting service.
Table 12-8
shows the allocation of CTM7 submodule
numbers and interrupt vector numbers.