
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
67
REV 1
Motorola, Inc. 1997
6/97
Quad 2-Channel Multiplexer
The MC74VHC157 is an advanced high speed CMOS quad 2–channel
multiplexer fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
It consists of four 2–input digital multiplexers with common select (S) and
enable (E) inputs. When E is held High, selection of data is inhibited and all
the outputs go Low.
The select decoding determines whether the A or B inputs get routed to
the corresponding Y outputs.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
High Speed: tPD = 4.1ns (Typ) at VCC = 5V
Low Power Dissipation: ICC = 4A (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2V to 5.5V Operating Range
Low Noise: VOLP = 0.8V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Chip Complexity: 82 FETs or 20 Equivalent Gates
EXPANDED LOGIC DIAGRAM
4
7
9
12
2
3
5
6
11
10
14
13
15
1
A0
B0
A1
B1
A2
B2
A3
B3
Y0
Y1
Y2
Y3
E
S
DATA
OUTPUTS
NIBBLE
INPUTS
FUNCTION TABLE
E
S
Y0 – Y3
A0 – A3, B0 – B3 = the levels of
the respective Data–Word Inputs.
H
L
X
L
H
L
A0 – A3
B0 – B3
Inputs
Outputs
MC74VHC157
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
S
Y0
B0
A0
Y1
B1
A1
GND
Y3
B3
A3
E
VCC
B2
A2
Y2
D SUFFIX
16–LEAD SOIC PACKAGE
CASE 751B–05
DT SUFFIX
16–LEAD TSSOP PACKAGE
CASE 948F–01
ORDERING INFORMATION
MC74VHCXXXD
MC74VHCXXXDT
MC74VHCXXXM
SOIC
TSSOP
SOIC EIAJ
M SUFFIX
16–LEAD SOIC EIAJ PACKAGE
CASE 966–01