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參數資料
型號: MC74ACT377NG
廠商: ON Semiconductor
文件頁數: 1/10頁
文件大小: 0K
描述: IC FLIP FLOP OCT D W/CLK 20-DIP
標準包裝: 18
系列: 74ACT
功能: 標準
類型: D 型總線
輸出類型: 非反相
元件數: 1
每個元件的位元數: 8
頻率 - 時鐘: 140MHz
延遲時間 - 傳輸: 3ns
觸發器類型: 正邊沿
輸出電流高,低: 24mA,24mA
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
Semiconductor Components Industries, LLC, 2006
December, 2006 Rev. 9
1
Publication Order Number:
MC74AC377/D
MC74AC377, MC74ACT377
Octal D FlipFlop with
Clock Enable
The MC74AC377/74ACT377 has eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously, when
the Clock Enable (CE) is LOW. The register is fully edge-triggered.
The state of each D input, one setup time before the LOW-to-HIGH
clock transition, is transferred to the corresponding flip-flop’s Q
output. The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
Features
Ideal for Addressable Register Applications
Clock Enable for Address and Data Synchronization Applications
Eight Edge-Triggered D Flip-Flops
Buffered Common Clock
Outputs Source/Sink 24 mA
See MC74AC273 for Master Reset Version
See MC74AC373 for Transparent Latch Version
See MC74AC374 for 3-State Version
ACT377 Has TTL Compatible Inputs
MSL = 1 for all Surface Mount
Chip Complexity: 292 FETs or 73 Gates
PbFree Packages are Available
19
20
18
17
16
15
14
2
1
34567
VCC
13
8
12
9
11
10
O7
D7
D6
O6
O5
D5
D4
O4
CP
CE
O0
D0
D1
O1
O2
D2
D3
O3
GND
Figure 1. Pinout: 20Lead Packages Conductors
(Top View)
PIN NAMES
PIN
FUNCTION
D0D7
Data Inputs
CE
Clock Enable (Active LOW)
Q0Q7
Data Outputs
CP
Clock Pulse Input
Figure 2. Logic Symbol
O0 O1 O2 O3 O4 O5 O6 O7
D0 D1 D2 D3 D4 D5 D6 D7
CP
CE
http://onsemi.com
SOIC20W
DW SUFFIX
CASE 751D
TSSOP20
DT SUFFIX
CASE 948E
SOEIAJ20
M SUFFIX
CASE 967
1
PDIP20
N SUFFIX
CASE 738
1
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
See general marking information in the device marking
section on page 7 of this data sheet.
DEVICE MARKING INFORMATION
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