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參數(shù)資料
| 型號(hào)： | MC74F160A |
| 廠商： | Motorola, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | SYNCHRONOUS PRESETTABLE BCD DECADE COUNTER |
| 中文描述： | 同步可預(yù)置BCD碼十進(jìn)制計(jì)數(shù)器 |
| 文件頁(yè)數(shù)： | 2/4頁(yè) |
| 文件大小： | 86K |
| 代理商： | MC74F160A |
4-72
FAST AND LS TTL DATA
MC74F160A
MC74F162A
CP
D
NOTE:
This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
LOGIC DIAGRAM
DETAIL A
DETAIL A
DETAIL A
DETAIL A
P0
P1
P3
P2
CEP
CET
CP
Q0
Q1
Q2
Q3
MR (MC74F160A)
SR (MC74F162A)
Q0
Q0
TC
CP
CP D
Q
Q
CD
MC74F160A
MC74F162A
MC74F162A
ONLY
MC74F160A
ONLY
PE
FUNCTIONAL DESCRIPTION
The MC74F160A and MC74F162A count modulo-10 in the
BCD (8421) sequence. From state 9 (HLLH) they increment
to state 0 (LLLL). The clock inputs of all flip-flops are driven in
parallel through a clock buffer. Thus, all changes of the Q out-
puts (except due to Master Reset of the MC74F160A) occur
as a result of, and synchronous with, the LOW-to-HIGH transi-
tion of the CP input signal. The circuits have four fundamental
modes of operation, in order of precedence: asynchronous re-
set (MC74F160A), synchronous reset (MC74F162A), paral-
lel load, count-up and hold. Five control inputs — Master Re-
set (MR, MC74F160A), Synchronous Reset (SR,
MC74F162A), Parallel Enable (PE), Count Enable Parallel
(CEP) and Count Enable Trickle (CET) — determine the mode
of operation, as shown in the Function Table. A LOW signal on
MR overrides all other inputs and asynchronously forces all
outputs LOW. A LOW signal on SR overrides counting and
parallel loading and allows all outputs to go LOW on the next
rising edge of CP. A LOW signal on PE overrides counting and
allows information on the Parallel Data (Pn) inputs to be
loaded into the flip-flops on the next rising edge of CP. With
PE and MR (MC74F160A) or SR (MC74F162A) HIGH, CEP
and CET permit counting when both are HIGH. Conversely, a
LOW signal on either CEP or CET inhibits counting.
The MC74F160A and MC74F162A use D-type edge-trig-
gered flip-flops and changing the SR, PE, CEP, and CET in-
puts when the CP is in either state does not cause errors, pro-
vided that the recommended setup and hold times, with
respect to the rising edge of CP, are observed.
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| MC74F162A | SYNCHRONOUS PRESETTABLE BCD DECADE COUNTER |
| MC74F162AD | SYNCHRONOUS PRESETTABLE BCD DECADE COUNTER |
| MC74F162AJ | SYNCHRONOUS PRESETTABLE BCD DECADE COUNTER |
| MC74F162AN | SYNCHRONOUS PRESETTABLE BCD DECADE COUNTER |
| MC74F160AJ | Processor Supervisory Circuits 5-SOT-23 -40 to 85 |
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